![Steven King](/assets/img/avatar_default.png)
Add support for the Coldfire 5441x (54410/54415/54416/54417/54418). Currently we only support noMMU mode. It requires the PIT patch posted previously as it uses the PIT instead of the dma timer as a clock source so we can get all that GENERIC_CLOCKEVENTS goodness. It also adds some simple clk definitions and very simple minded power management. The gpio code is tweeked and some additional devices are added to devices.c. The Makefile uses -mv4e as apparently, the only difference a v4m (m5441x) and a v4e is the later has a FPU, which I don't think should matter to us in the kernel. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
200 lines
4.8 KiB
C
200 lines
4.8 KiB
C
/*
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* intc-simr.c
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*
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* Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
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*
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* (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/traps.h>
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/*
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* The EDGE Port interrupts are the fixed 7 external interrupts.
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* They need some special treatment, for example they need to be acked.
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*/
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#ifdef CONFIG_M520x
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/*
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* The 520x parts only support a limited range of these external
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* interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
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*/
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#define EINT0 64 /* Is not actually used, but spot reserved for it */
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#define EINT1 65 /* EDGE Port interrupt 1 */
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#define EINT4 66 /* EDGE Port interrupt 4 */
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#define EINT7 67 /* EDGE Port interrupt 7 */
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static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
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static unsigned int inline irq2ebit(unsigned int irq)
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{
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return irqebitmap[irq - EINT0];
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}
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#else
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/*
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* Most of the ColdFire parts with the EDGE Port module just have
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* a strait direct mapping of the 7 external interrupts. Although
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* there is a bit reserved for 0, it is not used.
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*/
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#define EINT0 64 /* Is not actually used, but spot reserved for it */
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#define EINT1 65 /* EDGE Port interrupt 1 */
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#define EINT7 71 /* EDGE Port interrupt 7 */
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static unsigned int inline irq2ebit(unsigned int irq)
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{
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return irq - EINT0;
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}
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#endif
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/*
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* There maybe one, two or three interrupt control units, each has 64
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* interrupts. If there is no second or third unit then MCFINTC1_* or
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* MCFINTC2_* defines will be 0 (and code for them optimized away).
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*/
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static void intc_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - MCFINT_VECBASE;
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if (MCFINTC2_SIMR && (irq > 128))
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__raw_writeb(irq - 128, MCFINTC2_SIMR);
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else if (MCFINTC1_SIMR && (irq > 64))
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__raw_writeb(irq - 64, MCFINTC1_SIMR);
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else
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__raw_writeb(irq, MCFINTC0_SIMR);
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}
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static void intc_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - MCFINT_VECBASE;
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if (MCFINTC2_CIMR && (irq > 128))
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__raw_writeb(irq - 128, MCFINTC2_CIMR);
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else if (MCFINTC1_CIMR && (irq > 64))
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__raw_writeb(irq - 64, MCFINTC1_CIMR);
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else
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__raw_writeb(irq, MCFINTC0_CIMR);
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}
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static void intc_irq_ack(struct irq_data *d)
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{
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unsigned int ebit = irq2ebit(d->irq);
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__raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
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}
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static unsigned int intc_irq_startup(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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if ((irq >= EINT1) && (irq <= EINT7)) {
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unsigned int ebit = irq2ebit(irq);
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u8 v;
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#if defined(MCFEPORT_EPDDR)
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/* Set EPORT line as input */
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v = __raw_readb(MCFEPORT_EPDDR);
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__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
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#endif
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/* Set EPORT line as interrupt source */
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v = __raw_readb(MCFEPORT_EPIER);
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__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
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}
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irq -= MCFINT_VECBASE;
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if (MCFINTC2_ICR0 && (irq > 128))
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__raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
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else if (MCFINTC1_ICR0 && (irq > 64))
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__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
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else
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__raw_writeb(5, MCFINTC0_ICR0 + irq);
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intc_irq_unmask(d);
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return 0;
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}
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static int intc_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int ebit, irq = d->irq;
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u16 pa, tb;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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tb = 0x1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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tb = 0x2;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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tb = 0x3;
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break;
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default:
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/* Level triggered */
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tb = 0;
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break;
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}
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if (tb)
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irq_set_handler(irq, handle_edge_irq);
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ebit = irq2ebit(irq) * 2;
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pa = __raw_readw(MCFEPORT_EPPAR);
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pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
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__raw_writew(pa, MCFEPORT_EPPAR);
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return 0;
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}
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static struct irq_chip intc_irq_chip = {
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.name = "CF-INTC",
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.irq_startup = intc_irq_startup,
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.irq_mask = intc_irq_mask,
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.irq_unmask = intc_irq_unmask,
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};
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static struct irq_chip intc_irq_chip_edge_port = {
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.name = "CF-INTC-EP",
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.irq_startup = intc_irq_startup,
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.irq_mask = intc_irq_mask,
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.irq_unmask = intc_irq_unmask,
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.irq_ack = intc_irq_ack,
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.irq_set_type = intc_irq_set_type,
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};
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void __init init_IRQ(void)
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{
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int irq, eirq;
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/* Mask all interrupt sources */
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__raw_writeb(0xff, MCFINTC0_SIMR);
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if (MCFINTC1_SIMR)
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__raw_writeb(0xff, MCFINTC1_SIMR);
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if (MCFINTC2_SIMR)
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__raw_writeb(0xff, MCFINTC2_SIMR);
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eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
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(MCFINTC2_ICR0 ? 64 : 0);
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for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
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if ((irq >= EINT1) && (irq <= EINT7))
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irq_set_chip(irq, &intc_irq_chip_edge_port);
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else
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irq_set_chip(irq, &intc_irq_chip);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
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irq_set_handler(irq, handle_level_irq);
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}
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}
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