![Marc Zyngier](/assets/img/avatar_default.png)
Commit 9a1091ef00
("irqchip: gic: Support hierarchy irq domain")
changed the GIC driver to use a non-legacy IRQ domain on DT
platforms. This patch assumes that DT-driven systems are getting
all of their interrupts from device tree.
Turns out that OMAP has quite a few hidden gems, and still uses
hardcoded interrupts despite having fairly complete DTs.
This patch attempts to work around these by offering a translation
method that can be called directly from the hwmod code, if present.
The same hack is sprinkled over PRCM and TWL.
It isn't pretty, but it seems to do the job without having to add
more hacks to the interrupt controller code.
Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Nishanth Menon <nm@ti.com>
[tony@atomide.com: updated to fix make randconfig issue]
Signed-off-by: Tony Lindgren <tony@atomide.com>
771 lines
22 KiB
C
771 lines
22 KiB
C
/*
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* OMAP4 PRM module functions
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*
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* Copyright (C) 2011-2012 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* BenoƮt Cousson
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include "soc.h"
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#include "iomap.h"
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#include "common.h"
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#include "vp.h"
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "prcm44xx.h"
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#include "prminst44xx.h"
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#include "powerdomain.h"
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/* Static data */
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static void omap44xx_prm_read_pending_irqs(unsigned long *events);
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static void omap44xx_prm_ocp_barrier(void);
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static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
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static void omap44xx_prm_restore_irqen(u32 *saved_mask);
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static void omap44xx_prm_reconfigure_io_chain(void);
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static const struct omap_prcm_irq omap4_prcm_irqs[] = {
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OMAP_PRCM_IRQ("io", 9, 1),
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};
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static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
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.ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
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.nr_regs = 2,
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.irqs = omap4_prcm_irqs,
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.nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
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.irq = 11 + OMAP44XX_IRQ_GIC_START,
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.xlate_irq = omap4_xlate_irq,
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.read_pending_irqs = &omap44xx_prm_read_pending_irqs,
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.ocp_barrier = &omap44xx_prm_ocp_barrier,
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.save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
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.restore_irqen = &omap44xx_prm_restore_irqen,
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.reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
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};
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/*
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* omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
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* hardware register (which are specific to OMAP44xx SoCs) to reset
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* source ID bit shifts (which is an OMAP SoC-independent
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* enumeration)
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*/
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static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
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{ OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
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OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
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{ OMAP4430_GLOBAL_COLD_RST_SHIFT,
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OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
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{ OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
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OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
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{ OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
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{ OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
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{ OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
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{ OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
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OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
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{ OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
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OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
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{ OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
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OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
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{ OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
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{ OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
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{ -1, -1 },
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};
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/* PRM low-level functions */
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/* Read a register in a CM/PRM instance in the PRM module */
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static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
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{
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return readl_relaxed(prm_base + inst + reg);
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}
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/* Write into a register in a CM/PRM instance in the PRM module */
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static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
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{
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writel_relaxed(val, prm_base + inst + reg);
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
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{
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u32 v;
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v = omap4_prm_read_inst_reg(inst, reg);
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v &= ~mask;
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v |= bits;
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omap4_prm_write_inst_reg(v, inst, reg);
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return v;
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}
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/* PRM VP */
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/*
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* struct omap4_vp - OMAP4 VP register access description.
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* @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
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*/
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struct omap4_vp {
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u32 irqstatus_mpu;
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u32 tranxdone_status;
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};
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static struct omap4_vp omap4_vp[] = {
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[OMAP4_VP_VDD_MPU_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
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.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_IVA_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
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},
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[OMAP4_VP_VDD_CORE_ID] = {
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.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
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.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
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},
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};
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u32 omap4_prm_vp_check_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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u32 irqstatus;
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irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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return irqstatus & vp->tranxdone_status;
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}
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void omap4_prm_vp_clear_txdone(u8 vp_id)
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{
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struct omap4_vp *vp = &omap4_vp[vp_id];
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omap4_prminst_write_inst_reg(vp->tranxdone_status,
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OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_OCP_SOCKET_INST,
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vp->irqstatus_mpu);
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};
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u32 omap4_prm_vcvp_read(u8 offset)
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{
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return 0;
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return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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inst, offset);
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}
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void omap4_prm_vcvp_write(u32 val, u8 offset)
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{
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return;
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omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
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inst, offset);
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}
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u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
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{
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return 0;
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return omap4_prminst_rmw_inst_reg_bits(mask, bits,
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OMAP4430_PRM_PARTITION,
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inst,
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offset);
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}
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static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
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{
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u32 mask, st;
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/* XXX read mask from RAM? */
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mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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irqen_offs);
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st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
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return mask & st;
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}
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/**
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* omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
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* @events: ptr to two consecutive u32s, preallocated by caller
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*
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* Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
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* MPU IRQs, and store the result into the two u32s pointed to by @events.
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* No return value.
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*/
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static void omap44xx_prm_read_pending_irqs(unsigned long *events)
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{
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events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
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OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
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}
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/**
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* omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
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*
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* Force any buffered writes to the PRM IP block to complete. Needed
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* by the PRM IRQ handler, which reads and writes directly to the IP
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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static void omap44xx_prm_ocp_barrier(void)
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{
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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/**
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* omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
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* @saved_mask: ptr to a u32 array to save IRQENABLE bits
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*
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* Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
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* @saved_mask. @saved_mask must be allocated by the caller.
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* Intended to be used in the PRM interrupt handler suspend callback.
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* The OCP barrier is needed to ensure the write to disable PRM
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* interrupts reaches the PRM before returning; otherwise, spurious
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* interrupts might occur. No return value.
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*/
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static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] =
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
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saved_mask[1] =
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
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omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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/* OCP barrier */
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omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_REVISION_PRM_OFFSET);
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}
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/**
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* omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
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* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
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*
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* Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
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* @saved_mask. Intended to be used in the PRM interrupt handler resume
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* callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
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* No OCP barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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static void omap44xx_prm_restore_irqen(u32 *saved_mask)
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{
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omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_OFFSET);
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omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
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OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
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}
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/**
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* omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
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*
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* Clear any previously-latched I/O wakeup events and ensure that the
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* I/O wakeup gates are aligned with the current mux settings. Works
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* by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
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* deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
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* No return value. XXX Are the final two steps necessary?
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*/
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static void omap44xx_prm_reconfigure_io_chain(void)
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{
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int i = 0;
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return;
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/* Trigger WUCLKIN enable */
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omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
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OMAP4430_WUCLK_CTRL_MASK,
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inst,
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OMAP4_PRM_IO_PMCTRL_OFFSET);
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omap_test_timeout(
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(((omap4_prm_read_inst_reg(inst,
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OMAP4_PRM_IO_PMCTRL_OFFSET) &
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OMAP4430_WUCLK_STATUS_MASK) >>
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OMAP4430_WUCLK_STATUS_SHIFT) == 1),
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MAX_IOPAD_LATCH_TIME, i);
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if (i == MAX_IOPAD_LATCH_TIME)
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pr_warn("PRM: I/O chain clock line assertion timed out\n");
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/* Trigger WUCLKIN disable */
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omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
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inst,
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OMAP4_PRM_IO_PMCTRL_OFFSET);
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omap_test_timeout(
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(((omap4_prm_read_inst_reg(inst,
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OMAP4_PRM_IO_PMCTRL_OFFSET) &
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OMAP4430_WUCLK_STATUS_MASK) >>
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OMAP4430_WUCLK_STATUS_SHIFT) == 0),
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MAX_IOPAD_LATCH_TIME, i);
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if (i == MAX_IOPAD_LATCH_TIME)
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pr_warn("PRM: I/O chain clock line deassertion timed out\n");
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return;
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}
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/**
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* omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
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*
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* Activates the I/O wakeup event latches and allows events logged by
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* those latches to signal a wakeup event to the PRCM. For I/O wakeups
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* to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
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* omap44xx_prm_reconfigure_io_chain() must be called. No return value.
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*/
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static void __init omap44xx_prm_enable_io_wakeup(void)
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{
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return;
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omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
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OMAP4430_GLOBAL_WUEN_MASK,
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inst,
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OMAP4_PRM_IO_PMCTRL_OFFSET);
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}
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/**
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* omap44xx_prm_read_reset_sources - return the last SoC reset source
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*
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* Return a u32 representing the last reset sources of the SoC. The
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* returned reset source bits are standardized across OMAP SoCs.
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*/
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static u32 omap44xx_prm_read_reset_sources(void)
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{
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struct prm_reset_src_map *p;
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u32 r = 0;
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u32 v;
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s32 inst = omap4_prmst_get_prm_dev_inst();
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if (inst == PRM_INSTANCE_UNKNOWN)
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return 0;
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v = omap4_prm_read_inst_reg(inst,
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OMAP4_RM_RSTST);
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p = omap44xx_prm_reset_src_map;
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while (p->reg_shift >= 0 && p->std_shift >= 0) {
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if (v & (1 << p->reg_shift))
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r |= 1 << p->std_shift;
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p++;
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}
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return r;
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}
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/**
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* omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
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* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
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* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
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* @idx: CONTEXT register offset
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*
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* Return 1 if any bits were set in the *_CONTEXT_* register
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* identified by (@part, @inst, @idx), which means that some context
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* was lost for that module; otherwise, return 0.
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*/
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static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
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{
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return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
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}
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/**
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* omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
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* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
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* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
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* @idx: CONTEXT register offset
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*
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* Clear hardware context loss bits for the module identified by
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* (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
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* is there a way to avoid this?
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*/
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static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
|
|
u16 idx)
|
|
{
|
|
omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
|
|
}
|
|
|
|
/* Powerdomain low-level functions */
|
|
|
|
static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
|
|
{
|
|
omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
|
|
(pwrst << OMAP_POWERSTATE_SHIFT),
|
|
pwrdm->prcm_partition,
|
|
pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
u32 v;
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
v &= OMAP_POWERSTATE_MASK;
|
|
v >>= OMAP_POWERSTATE_SHIFT;
|
|
|
|
return v;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
u32 v;
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTST);
|
|
v &= OMAP_POWERSTATEST_MASK;
|
|
v >>= OMAP_POWERSTATEST_SHIFT;
|
|
|
|
return v;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
u32 v;
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTST);
|
|
v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
|
|
v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
|
|
|
|
return v;
|
|
}
|
|
|
|
static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
|
|
{
|
|
omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
|
|
(1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
|
|
pwrdm->prcm_partition,
|
|
pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
|
|
OMAP4430_LASTPOWERSTATEENTERED_MASK,
|
|
pwrdm->prcm_partition,
|
|
pwrdm->prcm_offs, OMAP4_PM_PWSTST);
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
|
|
{
|
|
u32 v;
|
|
|
|
v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
|
|
omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
|
|
pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
|
|
u8 pwrst)
|
|
{
|
|
u32 m;
|
|
|
|
m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
|
|
|
|
omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
|
|
pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
|
|
u8 pwrst)
|
|
{
|
|
u32 m;
|
|
|
|
m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
|
|
|
|
omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
|
|
pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
u32 v;
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTST);
|
|
v &= OMAP4430_LOGICSTATEST_MASK;
|
|
v >>= OMAP4430_LOGICSTATEST_SHIFT;
|
|
|
|
return v;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
|
|
{
|
|
u32 v;
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
v &= OMAP4430_LOGICRETSTATE_MASK;
|
|
v >>= OMAP4430_LOGICRETSTATE_SHIFT;
|
|
|
|
return v;
|
|
}
|
|
|
|
/**
|
|
* omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
|
|
* @pwrdm: struct powerdomain * to read the state for
|
|
*
|
|
* Reads the previous logic powerstate for a powerdomain. This
|
|
* function must determine the previous logic powerstate by first
|
|
* checking the previous powerstate for the domain. If that was OFF,
|
|
* then logic has been lost. If previous state was RETENTION, the
|
|
* function reads the setting for the next retention logic state to
|
|
* see the actual value. In every other case, the logic is
|
|
* retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
|
|
* depending whether the logic was retained or not.
|
|
*/
|
|
static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
|
|
{
|
|
int state;
|
|
|
|
state = omap4_pwrdm_read_prev_pwrst(pwrdm);
|
|
|
|
if (state == PWRDM_POWER_OFF)
|
|
return PWRDM_POWER_OFF;
|
|
|
|
if (state != PWRDM_POWER_RET)
|
|
return PWRDM_POWER_RET;
|
|
|
|
return omap4_pwrdm_read_logic_retst(pwrdm);
|
|
}
|
|
|
|
static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
|
|
{
|
|
u32 m, v;
|
|
|
|
m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTST);
|
|
v &= m;
|
|
v >>= __ffs(m);
|
|
|
|
return v;
|
|
}
|
|
|
|
static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
|
|
{
|
|
u32 m, v;
|
|
|
|
m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
|
|
|
|
v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTCTRL);
|
|
v &= m;
|
|
v >>= __ffs(m);
|
|
|
|
return v;
|
|
}
|
|
|
|
/**
|
|
* omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
|
|
* @pwrdm: struct powerdomain * to read mem powerstate for
|
|
* @bank: memory bank index
|
|
*
|
|
* Reads the previous memory powerstate for a powerdomain. This
|
|
* function must determine the previous memory powerstate by first
|
|
* checking the previous powerstate for the domain. If that was OFF,
|
|
* then logic has been lost. If previous state was RETENTION, the
|
|
* function reads the setting for the next memory retention state to
|
|
* see the actual value. In every other case, the logic is
|
|
* retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
|
|
* depending whether logic was retained or not.
|
|
*/
|
|
static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
|
|
{
|
|
int state;
|
|
|
|
state = omap4_pwrdm_read_prev_pwrst(pwrdm);
|
|
|
|
if (state == PWRDM_POWER_OFF)
|
|
return PWRDM_POWER_OFF;
|
|
|
|
if (state != PWRDM_POWER_RET)
|
|
return PWRDM_POWER_RET;
|
|
|
|
return omap4_pwrdm_read_mem_retst(pwrdm, bank);
|
|
}
|
|
|
|
static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
|
|
{
|
|
u32 c = 0;
|
|
|
|
/*
|
|
* REVISIT: pwrdm_wait_transition() may be better implemented
|
|
* via a callback and a periodic timer check -- how long do we expect
|
|
* powerdomain transitions to take?
|
|
*/
|
|
|
|
/* XXX Is this udelay() value meaningful? */
|
|
while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
|
|
pwrdm->prcm_offs,
|
|
OMAP4_PM_PWSTST) &
|
|
OMAP_INTRANSITION_MASK) &&
|
|
(c++ < PWRDM_TRANSITION_BAILOUT))
|
|
udelay(1);
|
|
|
|
if (c > PWRDM_TRANSITION_BAILOUT) {
|
|
pr_err("powerdomain: %s: waited too long to complete transition\n",
|
|
pwrdm->name);
|
|
return -EAGAIN;
|
|
}
|
|
|
|
pr_debug("powerdomain: completed transition in %d loops\n", c);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap4_check_vcvp(void)
|
|
{
|
|
if (prm_features & PRM_HAS_VOLTAGE)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct pwrdm_ops omap4_pwrdm_operations = {
|
|
.pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
|
|
.pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
|
|
.pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
|
|
.pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
|
|
.pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
|
|
.pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
|
|
.pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
|
|
.pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
|
|
.pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
|
|
.pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
|
|
.pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
|
|
.pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
|
|
.pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
|
|
.pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
|
|
.pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
|
|
.pwrdm_wait_transition = omap4_pwrdm_wait_transition,
|
|
.pwrdm_has_voltdm = omap4_check_vcvp,
|
|
};
|
|
|
|
static int omap44xx_prm_late_init(void);
|
|
|
|
/*
|
|
* XXX document
|
|
*/
|
|
static struct prm_ll_data omap44xx_prm_ll_data = {
|
|
.read_reset_sources = &omap44xx_prm_read_reset_sources,
|
|
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
|
|
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
|
|
.late_init = &omap44xx_prm_late_init,
|
|
.assert_hardreset = omap4_prminst_assert_hardreset,
|
|
.deassert_hardreset = omap4_prminst_deassert_hardreset,
|
|
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
|
|
.reset_system = omap4_prminst_global_warm_sw_reset,
|
|
};
|
|
|
|
int __init omap44xx_prm_init(void)
|
|
{
|
|
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
|
|
prm_features |= PRM_HAS_IO_WAKEUP;
|
|
|
|
if (!soc_is_dra7xx())
|
|
prm_features |= PRM_HAS_VOLTAGE;
|
|
|
|
return prm_register(&omap44xx_prm_ll_data);
|
|
}
|
|
|
|
static struct of_device_id omap_prm_dt_match_table[] = {
|
|
{ .compatible = "ti,omap4-prm" },
|
|
{ .compatible = "ti,omap5-prm" },
|
|
{ .compatible = "ti,dra7-prm" },
|
|
{ }
|
|
};
|
|
|
|
static int omap44xx_prm_late_init(void)
|
|
{
|
|
struct device_node *np;
|
|
int irq_num;
|
|
|
|
if (!(prm_features & PRM_HAS_IO_WAKEUP))
|
|
return 0;
|
|
|
|
/* OMAP4+ is DT only now */
|
|
if (!of_have_populated_dt())
|
|
return 0;
|
|
|
|
np = of_find_matching_node(NULL, omap_prm_dt_match_table);
|
|
|
|
if (!np) {
|
|
/* Default loaded up with OMAP4 values */
|
|
if (!cpu_is_omap44xx())
|
|
return 0;
|
|
} else {
|
|
irq_num = of_irq_get(np, 0);
|
|
/*
|
|
* Already have OMAP4 IRQ num. For all other platforms, we need
|
|
* IRQ numbers from DT
|
|
*/
|
|
if (irq_num < 0 && !cpu_is_omap44xx()) {
|
|
if (irq_num == -EPROBE_DEFER)
|
|
return irq_num;
|
|
|
|
/* Have nothing to do */
|
|
return 0;
|
|
}
|
|
|
|
/* Once OMAP4 DT is filled as well */
|
|
if (irq_num >= 0) {
|
|
omap4_prcm_irq_setup.irq = irq_num;
|
|
omap4_prcm_irq_setup.xlate_irq = NULL;
|
|
}
|
|
}
|
|
|
|
omap44xx_prm_enable_io_wakeup();
|
|
|
|
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
|
|
}
|
|
|
|
static void __exit omap44xx_prm_exit(void)
|
|
{
|
|
prm_unregister(&omap44xx_prm_ll_data);
|
|
}
|
|
__exitcall(omap44xx_prm_exit);
|