bd737fea4e
Like we are doing on DDR0 we need to cleanly shutdown DDR1 if it is used before rebooting. If DDR1 is not initialized, we check it and avoid dereferencing its address. Even by adding two more instructions, we are able to complete the procedure within a single cache line. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Olof Johansson <olof@lixom.net>
46 lines
1.2 KiB
ArmAsm
46 lines
1.2 KiB
ArmAsm
/*
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* reset AT91SAM9G45 as per errata
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*
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
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*
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* unless the SDRAM is cleanly shutdown before we hit the
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* reset register it can be left driving the data bus and
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* killing the chance of a subsequent boot from NAND
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*
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* GPLv2 Only
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*/
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#include <linux/linkage.h>
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#include <mach/hardware.h>
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#include <mach/at91_ramc.h>
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#include "at91_rstc.h"
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.arm
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/*
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* at91_ramc_base is an array void*
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* init at NULL if only one DDR controler is present in or DT
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*/
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.globl at91sam9g45_restart
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at91sam9g45_restart:
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ldr r5, =at91_ramc_base @ preload constants
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ldr r0, [r5]
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ldr r5, [r5, #4] @ ddr1
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cmp r5, #0
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ldr r4, =at91_rstc_base
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ldr r1, [r4]
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mov r2, #1
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mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
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ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
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.balign 32 @ align to cache line
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strne r2, [r5, #AT91_DDRSDRC_RTR] @ disable DDR1 access
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strne r3, [r5, #AT91_DDRSDRC_LPR] @ power down DDR1
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str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
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str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
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str r4, [r1, #AT91_RSTC_CR] @ reset processor
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b .
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