d7df84b3ce
Some irqchip initialization must be done on secondary CPUs. On mvebu platforms, this is currently achieved by having the arch/arm/mach-mvebu/platsmp.c code directly call into a function exported by the irqchip driver, which isn't really nice. This commit changes this by using the same solution as the one used in the GIC driver: the irqchip driver registers a CPU notifier, which is used to do the secondary CPU IRQ initialization. This way, the irqchip driver is completely autonomous, and the function no longer needs to be exposed from the irqchip driver to the SoC code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397483648-26611-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
28 lines
710 B
C
28 lines
710 B
C
/*
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* Generic definitions for Marvell Armada_370_XP SoCs
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_ARMADA_370_XP_H
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#define __MACH_ARMADA_370_XP_H
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#ifdef CONFIG_SMP
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#include <linux/cpumask.h>
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#define ARMADA_XP_MAX_CPUS 4
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void armada_xp_secondary_startup(void);
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extern struct smp_operations armada_xp_smp_ops;
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#endif
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#endif /* __MACH_ARMADA_370_XP_H */
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