9121dfca73
Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM change needed for one of the hwmod patches to function. Basic test logs for this branch on top of Tony's omap-for-v3.8/clock branch at commit558a0780b0are here: http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/ However, omap-for-v3.8/clock at558a0780does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/ which indicate that the series tests cleanly. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQs9J2AAoJEBvUPslcq6Vznz0QAM5Q8krs4fAZ35ekOnAAeh4a kWbkSq/VH74uPMbobUOeHVusJbfZBxm24CT/911wNXIHg/hku6WPhnQzStX2n/6w JKtHcQXeftgXecHBeyjDGdypcwknwTzIg78BECJi1FO+y/imaMjvxLDm74BXdBRF bLLmMLe2+Fnwz4IjwtOPz9mbje9NexMy+ppDyIVT36H+t9PQwDArOJMqLINWdioW e9LjUM4mr/5YZEOVu1tC30bJIcKq/m5yYS7dwifcSN67EsMUw90kQTKFtmNC2SzL DozIUHdsc990U65LhrH5EzoluT/tWPFl+ijkLmehfaVgSYIT5CmkDCgKUFNNY83r 7eVcPYvK8Nf2V8s0rMwy2mBy8j9p3Yug/kmOpRxdI90YCqxikJD5zdW+yQVX4qnt GXOyfw9BwK8g0Y7lEea1MN2s+y1E3n8EcaVyvQAW4N0wCkm3ELE6rm9HZoBXD3+d 4EovXn8DmTfvqiJ/M/FCqphyMMvp+NhO8Cg2vJUotEiCHdbIkaeXNI4AWg/sMlId aXUazd2i1WvynXvcSqJBbSKZQM+8GBPAuxqSQc8tP0JuOZo//sBYbXSUFClWksaw bvp+iJ6g/4/QqIG/B5EARSbkfCI1fTfTYObLe2Pd3cRdML3F0f/rCWRjPfl20BnQ weUVgyikcXT+aH2sfdIB =JSAM -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.8/devel-prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm2 From Tony Lindgren: omap prcm changes via Paul Walmsley <paul@pwsan.com>: Some miscellaneous OMAP hwmod changes for 3.8, along with a PRM change needed for one of the hwmod patches to function. Basic test logs for this branch on top of Tony's omap-for-v3.8/clock branch at commit558a0780b0are here: http://www.pwsan.com/omap/testlogs/hwmod_devel_a_3.8/20121121161522/ However, omap-for-v3.8/clock at558a0780does not include some fixes that are needed for a successful test. With several reverts, fixes, and workarounds applied, the following test logs were obtained: http://www.pwsan.com/omap/testlogs/TEST_hwmod_devel_a_3.8/20121121162719/ which indicate that the series tests cleanly. * tag 'omap-for-v3.8/devel-prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (49 commits) ARM: OMAP2+: omap_device: Correct resource handling for DT boot ARM: OMAP2+: hwmod: Add possibility to count hwmod resources based on type ARM: OMAP2+: hwmod: Add support for per hwmod/module context lost count ARM: OMAP2+: PRM: initialize some PRM functions early ARM: OMAP2+: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP2xxx: clock: drop obsolete clock data ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP3+: DPLL: drop !CONFIG_COMMON_CLK sections ARM: AM33xx: clock: drop obsolete clock data ARM: OMAP3xxx: clk: drop obsolete clock data ARM: OMAP3: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP44xx: clock: drop obsolete clock data ARM: OMAP4: clock: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP: hwmod: Cleanup !CONFIG_COMMON_CLK parts ARM: OMAP: clock: Switch to COMMON clk ARM: OMAP2: clock: Add 24xx data using common struct clk ARM: OMAP3: clock: Add 3xxx data using common struct clk ARM: AM33XX: clock: add clock data in common clock format ARM: OMAP4: clock: Add 44xx data using common struct clk ARM: OMAP2+: clock: add OMAP CCF convenience macros to mach-omap2/clock.h ... Some context conflicts due to nearby changes resolved in arch/arm/mach-omap2/io.c. Signed-off-by: Olof Johansson <olof@lixom.net>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/*
|
|
* OMAP34xx M2 divider clock code
|
|
*
|
|
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
|
* Copyright (C) 2007-2010 Nokia Corporation
|
|
*
|
|
* Paul Walmsley
|
|
* Jouni Högander
|
|
*
|
|
* Parts of this code are based on code written by
|
|
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#undef DEBUG
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/io.h>
|
|
|
|
#include "clock.h"
|
|
#include "clock3xxx.h"
|
|
#include "clock34xx.h"
|
|
#include "sdrc.h"
|
|
#include "sram.h"
|
|
|
|
#define CYCLES_PER_MHZ 1000000
|
|
|
|
/*
|
|
* CORE DPLL (DPLL3) M2 divider rate programming functions
|
|
*
|
|
* These call into SRAM code to do the actual CM writes, since the SDRAM
|
|
* is clocked from DPLL3.
|
|
*/
|
|
|
|
/**
|
|
* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
|
|
* @clk: struct clk * of DPLL to set
|
|
* @rate: rounded target rate
|
|
*
|
|
* Program the DPLL M2 divider with the rounded target rate. Returns
|
|
* -EINVAL upon error, or 0 upon success.
|
|
*/
|
|
int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
u32 new_div = 0;
|
|
u32 unlock_dll = 0;
|
|
u32 c;
|
|
unsigned long validrate, sdrcrate, _mpurate;
|
|
struct omap_sdrc_params *sdrc_cs0;
|
|
struct omap_sdrc_params *sdrc_cs1;
|
|
int ret;
|
|
unsigned long clkrate;
|
|
|
|
if (!clk || !rate)
|
|
return -EINVAL;
|
|
|
|
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
|
|
if (validrate != rate)
|
|
return -EINVAL;
|
|
|
|
sdrcrate = __clk_get_rate(sdrc_ick_p);
|
|
clkrate = __clk_get_rate(hw->clk);
|
|
if (rate > clkrate)
|
|
sdrcrate <<= ((rate / clkrate) >> 1);
|
|
else
|
|
sdrcrate >>= ((clkrate / rate) >> 1);
|
|
|
|
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
|
|
if (ret)
|
|
return -EINVAL;
|
|
|
|
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
|
|
pr_debug("clock: will unlock SDRC DLL\n");
|
|
unlock_dll = 1;
|
|
}
|
|
|
|
/*
|
|
* XXX This only needs to be done when the CPU frequency changes
|
|
*/
|
|
_mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
|
|
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
|
|
c += 1; /* for safety */
|
|
c *= SDRC_MPURATE_LOOPS;
|
|
c >>= SDRC_MPURATE_SCALE;
|
|
if (c == 0)
|
|
c = 1;
|
|
|
|
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
|
|
clkrate, validrate);
|
|
pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
|
|
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
|
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
|
|
if (sdrc_cs1)
|
|
pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
|
|
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
|
|
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
|
|
|
|
if (sdrc_cs1)
|
|
omap3_configure_core_dpll(
|
|
new_div, unlock_dll, c, rate > clkrate,
|
|
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
|
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
|
|
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
|
|
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
|
|
else
|
|
omap3_configure_core_dpll(
|
|
new_div, unlock_dll, c, rate > clkrate,
|
|
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
|
|
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
|
|
0, 0, 0, 0);
|
|
return 0;
|
|
}
|
|
|