cd6e9db277
Users of the CM funtionality should not access the CM registers directly by themselves. Thus, added new CM driver APIs for the OMAP2 specific functionalities which support the existing direct register accesses, and changed the platform code to use these. This is done in preparation for moving the CM code into its own individual driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* OMAP2xxx Clock Management (CM) register definitions
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*
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* Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The CM hardware modules on the OMAP2/3 are quite similar to each
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* other. The CM modules/instances on OMAP4 are quite different, so
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* they are handled in a separate file.
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*/
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#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
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#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
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#include "prcm-common.h"
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#include "cm2xxx_3xxx.h"
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#define OMAP2420_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
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#define OMAP2430_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
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/*
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* Module specific CM register offsets from CM_BASE + domain offset
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* Use cm_{read,write}_mod_reg() with these registers.
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* These register offsets generally appear in more than one PRCM submodule.
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*/
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/* OMAP2-specific register offsets */
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#define OMAP24XX_CM_FCLKEN2 0x0004
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#define OMAP24XX_CM_ICLKEN4 0x001c
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#define OMAP24XX_CM_AUTOIDLE4 0x003c
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#define OMAP24XX_CM_IDLEST4 0x002c
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/* CM_IDLEST bit field values to indicate deasserted IdleReq */
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#define OMAP24XX_CM_IDLEST_VAL 0
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/* Clock management domain register get/set */
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#ifndef __ASSEMBLER__
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extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
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extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
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extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
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extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
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extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
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extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
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extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
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extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
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extern bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
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extern int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
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u8 idlest_shift);
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extern int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
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s16 *prcm_inst, u8 *idlest_reg_id);
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extern int omap2xxx_cm_fclks_active(void);
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extern int omap2xxx_cm_mpu_retention_allowed(void);
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extern u32 omap2xxx_cm_get_core_clk_src(void);
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extern u32 omap2xxx_cm_get_core_pll_config(void);
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extern u32 omap2xxx_cm_get_pll_config(void);
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extern u32 omap2xxx_cm_get_pll_status(void);
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extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
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u32 mdm);
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extern int __init omap2xxx_cm_init(void);
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#endif
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#endif
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