b05ef2159d
These now come from device tree except for DSS and DMA that still uses hwmod to initialize. That will get fixed when we DSS gets device tree bindings and we move completely to the dmaengine API. Cc: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: updated to add trailing commas to structs] Signed-off-by: Tony Lindgren <tony@atomide.com>
725 lines
18 KiB
C
725 lines
18 KiB
C
/*
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* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
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*
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* Copyright (C) 2009-2011 Nokia Corporation
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX handle crossbar/shared link difference for L3?
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <linux/i2c-omap.h>
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#include <linux/platform_data/asoc-ti-mcbsp.h>
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#include <linux/platform_data/spi-omap2-mcspi.h>
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#include <linux/omap-dma.h>
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#include <linux/platform_data/mailbox-omap.h>
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#include <plat/dmtimer.h>
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#include "omap_hwmod.h"
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#include "mmc.h"
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#include "l3_2xxx.h"
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#include "soc.h"
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#include "omap_hwmod_common_data.h"
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#include "prm-regbits-24xx.h"
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#include "cm-regbits-24xx.h"
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#include "i2c.h"
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#include "wd_timer.h"
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/*
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* OMAP2430 hardware module integration data
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*
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* All of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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/*
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* IP blocks
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*/
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/* IVA2 (IVA2) */
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static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
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{ .name = "logic", .rst_shift = 0 },
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{ .name = "mmu", .rst_shift = 1 },
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};
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static struct omap_hwmod omap2430_iva_hwmod = {
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.name = "iva",
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.class = &iva_hwmod_class,
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.clkdm_name = "dsp_clkdm",
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.rst_lines = omap2430_iva_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
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.main_clk = "dsp_fck",
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};
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x20,
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.syss_offs = 0x10,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class i2c_class = {
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.name = "i2c",
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.sysc = &i2c_sysc,
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.rev = OMAP_I2C_IP_VERSION_1,
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.reset = &omap_i2c_reset,
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};
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static struct omap_i2c_dev_attr i2c_dev_attr = {
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.fifo_depth = 8, /* bytes */
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.flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
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OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
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};
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/* I2C1 */
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static struct omap_hwmod omap2430_i2c1_hwmod = {
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.name = "i2c1",
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.flags = HWMOD_16BIT_REG,
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.main_clk = "i2chs1_fck",
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.prcm = {
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.omap2 = {
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/*
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* NOTE: The CM_FCLKEN* and CM_ICLKEN* for
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* I2CHS IP's do not follow the usual pattern.
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* prcm_reg_id alone cannot be used to program
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* the iclk and fclk. Needs to be handled using
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* additional flags when clk handling is moved
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* to hwmod framework.
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*/
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
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},
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},
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.class = &i2c_class,
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.dev_attr = &i2c_dev_attr,
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};
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/* I2C2 */
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static struct omap_hwmod omap2430_i2c2_hwmod = {
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.name = "i2c2",
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.flags = HWMOD_16BIT_REG,
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.main_clk = "i2chs2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
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},
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},
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.class = &i2c_class,
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.dev_attr = &i2c_dev_attr,
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};
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/* gpio5 */
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static struct omap_hwmod omap2430_gpio5_hwmod = {
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.name = "gpio5",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "gpio5_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_GPIO5_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
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},
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},
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.class = &omap2xxx_gpio_hwmod_class,
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.dev_attr = &omap2xxx_gpio_dev_attr,
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};
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/* dma attributes */
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static struct omap_dma_dev_attr dma_dev_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
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.lch_count = 32,
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};
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static struct omap_hwmod omap2430_dma_system_hwmod = {
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.name = "dma",
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.class = &omap2xxx_dma_hwmod_class,
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.mpu_irqs = omap2_dma_system_irqs,
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.main_clk = "core_l3_ck",
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.dev_attr = &dma_dev_attr,
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.flags = HWMOD_NO_IDLEST,
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};
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/* mailbox */
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static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
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{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
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};
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static struct omap_mbox_pdata omap2430_mailbox_attrs = {
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.num_users = 4,
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.num_fifos = 6,
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.info_cnt = ARRAY_SIZE(omap2430_mailbox_info),
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.info = omap2430_mailbox_info,
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};
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static struct omap_hwmod omap2430_mailbox_hwmod = {
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.name = "mailbox",
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.class = &omap2xxx_mailbox_hwmod_class,
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.main_clk = "mailboxes_ick",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
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},
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},
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.dev_attr = &omap2430_mailbox_attrs,
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};
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/* mcspi3 */
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static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
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.num_chipselect = 2,
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};
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static struct omap_hwmod omap2430_mcspi3_hwmod = {
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.name = "mcspi3",
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.main_clk = "mcspi3_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
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},
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},
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.class = &omap2xxx_mcspi_class,
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.dev_attr = &omap_mcspi3_dev_attr,
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};
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/* usbhsotg */
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static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
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.rev_offs = 0x0400,
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.sysc_offs = 0x0404,
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.syss_offs = 0x0408,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class usbotg_class = {
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.name = "usbotg",
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.sysc = &omap2430_usbhsotg_sysc,
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};
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/* usb_otg_hs */
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static struct omap_hwmod omap2430_usbhsotg_hwmod = {
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.name = "usb_otg_hs",
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.main_clk = "usbhs_ick",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_USBHS_MASK,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
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},
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},
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.class = &usbotg_class,
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/*
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* Erratum ID: i479 idle_req / idle_ack mechanism potentially
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* broken when autoidle is enabled
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* workaround is to disable the autoidle bit at module level.
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*/
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.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
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| HWMOD_SWSUP_MSTANDBY,
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};
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/*
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* 'mcbsp' class
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* multi channel buffered serial port controller
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*/
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static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
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.rev_offs = 0x007C,
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.sysc_offs = 0x008C,
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.sysc_flags = (SYSC_HAS_SOFTRESET),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
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.name = "mcbsp",
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.sysc = &omap2430_mcbsp_sysc,
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.rev = MCBSP_CONFIG_TYPE2,
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};
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static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
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{ .role = "pad_fck", .clk = "mcbsp_clks" },
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{ .role = "prcm_fck", .clk = "func_96m_ck" },
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};
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/* mcbsp1 */
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static struct omap_hwmod omap2430_mcbsp1_hwmod = {
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.name = "mcbsp1",
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.class = &omap2430_mcbsp_hwmod_class,
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.main_clk = "mcbsp1_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp2 */
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static struct omap_hwmod omap2430_mcbsp2_hwmod = {
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.name = "mcbsp2",
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.class = &omap2430_mcbsp_hwmod_class,
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.main_clk = "mcbsp2_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp3 */
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static struct omap_hwmod omap2430_mcbsp3_hwmod = {
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.name = "mcbsp3",
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.class = &omap2430_mcbsp_hwmod_class,
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.main_clk = "mcbsp3_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_MCBSP3_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp4 */
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static struct omap_hwmod omap2430_mcbsp4_hwmod = {
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.name = "mcbsp4",
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.class = &omap2430_mcbsp_hwmod_class,
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.main_clk = "mcbsp4_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_MCBSP4_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp5 */
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static struct omap_hwmod omap2430_mcbsp5_hwmod = {
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.name = "mcbsp5",
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.class = &omap2430_mcbsp_hwmod_class,
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.main_clk = "mcbsp5_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP2430_EN_MCBSP5_SHIFT,
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.module_offs = CORE_MOD,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* MMC/SD/SDIO common */
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static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
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.rev_offs = 0x1fc,
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.sysc_offs = 0x10,
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.syss_offs = 0x14,
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2430_mmc_class = {
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.name = "mmc",
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.sysc = &omap2430_mmc_sysc,
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};
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/* MMC/SD/SDIO1 */
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static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
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{ .role = "dbck", .clk = "mmchsdb1_fck" },
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};
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static struct omap_mmc_dev_attr mmc1_dev_attr = {
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.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
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};
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static struct omap_hwmod omap2430_mmc1_hwmod = {
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.name = "mmc1",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.opt_clks = omap2430_mmc1_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
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.main_clk = "mmchs1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_MMCHS1_SHIFT,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
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},
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},
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.dev_attr = &mmc1_dev_attr,
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.class = &omap2430_mmc_class,
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};
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/* MMC/SD/SDIO2 */
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static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
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{ .role = "dbck", .clk = "mmchsdb2_fck" },
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};
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static struct omap_hwmod omap2430_mmc2_hwmod = {
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.name = "mmc2",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.opt_clks = omap2430_mmc2_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
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.main_clk = "mmchs2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 2,
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.module_bit = OMAP2430_EN_MMCHS2_SHIFT,
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.idlest_reg_id = 2,
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.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
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},
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},
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.class = &omap2430_mmc_class,
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};
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/* HDQ1W/1-wire */
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static struct omap_hwmod omap2430_hdq1w_hwmod = {
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.name = "hdq1w",
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.main_clk = "hdq_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_HDQ_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
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},
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},
|
|
.class = &omap2_hdq1w_class,
|
|
};
|
|
|
|
/*
|
|
* interfaces
|
|
*/
|
|
|
|
/* L3 -> L4_CORE interface */
|
|
/* l3_core -> usbhsotg interface */
|
|
static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
|
|
.master = &omap2430_usbhsotg_hwmod,
|
|
.slave = &omap2xxx_l3_main_hwmod,
|
|
.clk = "core_l3_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* L4 CORE -> I2C1 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_i2c1_hwmod,
|
|
.clk = "i2c1_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* L4 CORE -> I2C2 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_i2c2_hwmod,
|
|
.clk = "i2c2_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core ->usbhsotg interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_usbhsotg_hwmod,
|
|
.clk = "usb_l4_ick",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* L4 CORE -> MMC1 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mmc1_hwmod,
|
|
.clk = "mmchs1_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* L4 CORE -> MMC2 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mmc2_hwmod,
|
|
.clk = "mmchs2_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4 core -> mcspi3 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcspi3_hwmod,
|
|
.clk = "mcspi3_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* IVA2 <- L3 interface */
|
|
static struct omap_hwmod_ocp_if omap2430_l3__iva = {
|
|
.master = &omap2xxx_l3_main_hwmod,
|
|
.slave = &omap2430_iva_hwmod,
|
|
.clk = "core_l3_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> timer1 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_timer1_hwmod,
|
|
.clk = "gpt1_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> wd_timer2 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_wd_timer2_hwmod,
|
|
.clk = "mpu_wdt_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio1 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_gpio1_hwmod,
|
|
.clk = "gpios_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio2 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_gpio2_hwmod,
|
|
.clk = "gpios_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio3 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_gpio3_hwmod,
|
|
.clk = "gpios_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio4 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_gpio4_hwmod,
|
|
.clk = "gpios_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> gpio5 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_gpio5_hwmod,
|
|
.clk = "gpio5_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dma_system -> L3 */
|
|
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
|
|
.master = &omap2430_dma_system_hwmod,
|
|
.slave = &omap2xxx_l3_main_hwmod,
|
|
.clk = "core_l3_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> dma_system */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_dma_system_hwmod,
|
|
.clk = "sdma_ick",
|
|
.addr = omap2_dma_system_addrs,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mailbox */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mailbox_hwmod,
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp1 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcbsp1_hwmod,
|
|
.clk = "mcbsp1_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp2 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcbsp2_hwmod,
|
|
.clk = "mcbsp2_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp3 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcbsp3_hwmod,
|
|
.clk = "mcbsp3_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp4 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcbsp4_hwmod,
|
|
.clk = "mcbsp4_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> mcbsp5 */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_mcbsp5_hwmod,
|
|
.clk = "mcbsp5_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_core -> hdq1w */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
|
|
.master = &omap2xxx_l4_core_hwmod,
|
|
.slave = &omap2430_hdq1w_hwmod,
|
|
.clk = "hdq_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
|
|
};
|
|
|
|
/* l4_wkup -> 32ksync_counter */
|
|
static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
|
|
.master = &omap2xxx_l4_wkup_hwmod,
|
|
.slave = &omap2xxx_counter_32k_hwmod,
|
|
.clk = "sync_32k_ick",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
|
|
.master = &omap2xxx_l3_main_hwmod,
|
|
.slave = &omap2xxx_gpmc_hwmod,
|
|
.clk = "core_l3_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
|
|
&omap2xxx_l3_main__l4_core,
|
|
&omap2xxx_mpu__l3_main,
|
|
&omap2xxx_dss__l3,
|
|
&omap2430_usbhsotg__l3,
|
|
&omap2430_l4_core__i2c1,
|
|
&omap2430_l4_core__i2c2,
|
|
&omap2xxx_l4_core__l4_wkup,
|
|
&omap2_l4_core__uart1,
|
|
&omap2_l4_core__uart2,
|
|
&omap2_l4_core__uart3,
|
|
&omap2430_l4_core__usbhsotg,
|
|
&omap2430_l4_core__mmc1,
|
|
&omap2430_l4_core__mmc2,
|
|
&omap2xxx_l4_core__mcspi1,
|
|
&omap2xxx_l4_core__mcspi2,
|
|
&omap2430_l4_core__mcspi3,
|
|
&omap2430_l3__iva,
|
|
&omap2430_l4_wkup__timer1,
|
|
&omap2xxx_l4_core__timer2,
|
|
&omap2xxx_l4_core__timer3,
|
|
&omap2xxx_l4_core__timer4,
|
|
&omap2xxx_l4_core__timer5,
|
|
&omap2xxx_l4_core__timer6,
|
|
&omap2xxx_l4_core__timer7,
|
|
&omap2xxx_l4_core__timer8,
|
|
&omap2xxx_l4_core__timer9,
|
|
&omap2xxx_l4_core__timer10,
|
|
&omap2xxx_l4_core__timer11,
|
|
&omap2xxx_l4_core__timer12,
|
|
&omap2430_l4_wkup__wd_timer2,
|
|
&omap2xxx_l4_core__dss,
|
|
&omap2xxx_l4_core__dss_dispc,
|
|
&omap2xxx_l4_core__dss_rfbi,
|
|
&omap2xxx_l4_core__dss_venc,
|
|
&omap2430_l4_wkup__gpio1,
|
|
&omap2430_l4_wkup__gpio2,
|
|
&omap2430_l4_wkup__gpio3,
|
|
&omap2430_l4_wkup__gpio4,
|
|
&omap2430_l4_core__gpio5,
|
|
&omap2430_dma_system__l3,
|
|
&omap2430_l4_core__dma_system,
|
|
&omap2430_l4_core__mailbox,
|
|
&omap2430_l4_core__mcbsp1,
|
|
&omap2430_l4_core__mcbsp2,
|
|
&omap2430_l4_core__mcbsp3,
|
|
&omap2430_l4_core__mcbsp4,
|
|
&omap2430_l4_core__mcbsp5,
|
|
&omap2430_l4_core__hdq1w,
|
|
&omap2xxx_l4_core__rng,
|
|
&omap2xxx_l4_core__sham,
|
|
&omap2xxx_l4_core__aes,
|
|
&omap2430_l4_wkup__counter_32k,
|
|
&omap2430_l3__gpmc,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap2430_hwmod_init(void)
|
|
{
|
|
omap_hwmod_init();
|
|
return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
|
|
}
|