3b8c4ebb76
While debugging legacy mode vs device tree booted PM regressions, I noticed that omap3 is not toggling sys_clkreq and sys_off_mode pins like it should. The sys_clkreq and sys_off_mode pins are not toggling because of the following issues: 1. The default polarity for the sys_off_mode pin is wrong. OFFMODE_POL needs to be cleared for sys_off_mode to go down when hitting off-idle, while CLKREQ_POL needs to be set so sys_clkreq goes down when hitting retention. 2. The values for voltctrl register need to be updated dynamically. We need to set either the retention idle bits, or off idle bits in the voltctrl register depending the idle mode we're targeting to hit. Let's fix these two issues as otherwise the system will just hang if any twl4030 PMIC idle scripts are loaded. The only case where the system does not hang is if only retention idle over I2C4 is configured by the bootloader. Note that even without the twl4030 PMIC scripts, these fixes will do the proper signaling of sys_clkreq and sys_off_mode pins, so the fixes are needed to fix monitoring of PM states with LEDs or an oscilloscope. Cc: Kevin Hilman <khilman@linaro.org> Cc: Nishanth Menon <nm@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
135 lines
4.4 KiB
C
135 lines
4.4 KiB
C
/*
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* OMAP3/4 Voltage Controller (VC) structure and macro definitions
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*
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* Copyright (C) 2007, 2010 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Lesly A M <x0080970@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008, 2011 Nokia Corporation
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* Kalle Jokiniemi
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_VC_H
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#define __ARCH_ARM_MACH_OMAP2_VC_H
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#include <linux/kernel.h>
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struct voltagedomain;
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/**
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* struct omap_vc_common - per-VC register/bitfield data
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* @cmd_on_mask: ON bitmask in PRM_VC_CMD_VAL* register
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* @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
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* @bypass_val_reg: Offset of PRM_VC_BYPASS_VAL reg from PRM start
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* @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
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* @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
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* @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
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* @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
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* @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
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* @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
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* @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
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* @i2c_cfg_reg: I2C configuration register offset
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* @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
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* @i2c_mcode_mask: MCODE field mask for I2C config register
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*
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* XXX One of cmd_on_mask and cmd_on_shift are not needed
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* XXX VALID should probably be a shift, not a mask
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*/
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struct omap_vc_common {
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u32 cmd_on_mask;
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u32 valid;
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u8 bypass_val_reg;
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u8 data_shift;
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u8 slaveaddr_shift;
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u8 regaddr_shift;
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u8 cmd_on_shift;
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u8 cmd_onlp_shift;
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u8 cmd_ret_shift;
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u8 cmd_off_shift;
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u8 i2c_cfg_reg;
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u8 i2c_cfg_hsen_mask;
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u8 i2c_mcode_mask;
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};
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/* omap_vc_channel.flags values */
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#define OMAP_VC_CHANNEL_DEFAULT BIT(0)
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#define OMAP_VC_CHANNEL_CFG_MUTANT BIT(1)
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/**
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* struct omap_vc_channel - VC per-instance data
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* @i2c_slave_addr: I2C slave address of PMIC for this VC channel
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* @volt_reg_addr: voltage configuration register address
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* @cmd_reg_addr: command configuration register address
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* @setup_time: setup time (in sys_clk cycles) of regulator for this channel
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* @cfg_channel: current value of VC channel configuration register
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* @i2c_high_speed: whether or not to use I2C high-speed mode
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*
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* @common: pointer to VC common data for this platform
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* @smps_sa_mask: i2c slave address bitmask in the PRM_VC_SMPS_SA register
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* @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
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* @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
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* @cmdval_reg: register for on/ret/off voltage level values for this channel
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* @smps_sa_reg: Offset of PRM_VC_SMPS_SA reg from PRM start
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* @smps_volra_reg: Offset of PRM_VC_SMPS_VOL_RA reg from PRM start
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* @smps_cmdra_reg: Offset of PRM_VC_SMPS_CMD_RA reg from PRM start
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* @cfg_channel_reg: VC channel configuration register
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* @cfg_channel_sa_shift: bit shift for slave address cfg_channel register
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* @flags: VC channel-specific flags (optional)
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*/
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struct omap_vc_channel {
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/* channel state */
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u16 i2c_slave_addr;
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u16 volt_reg_addr;
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u16 cmd_reg_addr;
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u8 cfg_channel;
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bool i2c_high_speed;
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/* register access data */
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const struct omap_vc_common *common;
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u32 smps_sa_mask;
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u32 smps_volra_mask;
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u32 smps_cmdra_mask;
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u8 cmdval_reg;
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u8 smps_sa_reg;
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u8 smps_volra_reg;
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u8 smps_cmdra_reg;
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u8 cfg_channel_reg;
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u8 cfg_channel_sa_shift;
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u8 flags;
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};
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extern struct omap_vc_channel omap3_vc_mpu;
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extern struct omap_vc_channel omap3_vc_core;
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extern struct omap_vc_channel omap4_vc_mpu;
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extern struct omap_vc_channel omap4_vc_iva;
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extern struct omap_vc_channel omap4_vc_core;
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extern struct omap_vc_param omap3_mpu_vc_data;
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extern struct omap_vc_param omap3_core_vc_data;
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extern struct omap_vc_param omap4_mpu_vc_data;
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extern struct omap_vc_param omap4_iva_vc_data;
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extern struct omap_vc_param omap4_core_vc_data;
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void omap3_vc_set_pmic_signaling(int core_next_state);
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void omap_vc_init_channel(struct voltagedomain *voltdm);
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int omap_vc_pre_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 *target_vsel, u8 *current_vsel);
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void omap_vc_post_scale(struct voltagedomain *voltdm,
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unsigned long target_volt,
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u8 target_vsel, u8 current_vsel);
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int omap_vc_bypass_scale(struct voltagedomain *voltdm,
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unsigned long target_volt);
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#endif
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