1802d0beec
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
335 lines
10 KiB
C
335 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include "mtk_hdmi_phy.h"
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#define HDMI_CON0 0x00
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#define RG_HDMITX_PLL_EN BIT(31)
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#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
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#define PLL_FBKDIV_SHIFT 24
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#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
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#define PLL_FBKSEL_SHIFT 22
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#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
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#define PREDIV_SHIFT 20
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#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
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#define POSDIV_SHIFT 18
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#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
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#define RG_HDMITX_PLL_IR (0xf << 12)
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#define PLL_IR_SHIFT 12
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#define RG_HDMITX_PLL_IC (0xf << 8)
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#define PLL_IC_SHIFT 8
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#define RG_HDMITX_PLL_BP (0xf << 4)
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#define PLL_BP_SHIFT 4
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#define RG_HDMITX_PLL_BR (0x3 << 2)
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#define PLL_BR_SHIFT 2
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#define RG_HDMITX_PLL_BC (0x3 << 0)
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#define PLL_BC_SHIFT 0
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#define HDMI_CON1 0x04
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#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
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#define PLL_DIVEN_SHIFT 29
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#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
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#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
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#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
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#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
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#define RG_HDMITX_PLL_BAND (0x3f << 16)
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#define RG_HDMITX_PLL_REF_SEL BIT(15)
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#define RG_HDMITX_PLL_BIAS_EN BIT(14)
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#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
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#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
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#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
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#define PLL_TXDIV_SHIFT 10
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#define RG_HDMITX_PLL_LVROD_EN BIT(9)
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#define RG_HDMITX_PLL_MONVC_EN BIT(8)
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#define RG_HDMITX_PLL_MONCK_EN BIT(7)
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#define RG_HDMITX_PLL_MONREF_EN BIT(6)
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#define RG_HDMITX_PLL_TST_EN BIT(5)
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#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
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#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
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#define HDMI_CON2 0x08
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#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
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#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
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#define RG_HDMITX_EN_TX_CKLDO BIT(0)
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#define HDMI_CON3 0x0c
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#define RG_HDMITX_SER_EN (0xf << 28)
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#define RG_HDMITX_PRD_EN (0xf << 24)
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#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
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#define RG_HDMITX_DRV_EN (0xf << 16)
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#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
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#define DRV_IMP_EN_SHIFT 12
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#define RG_HDMITX_MHLCK_FORCE BIT(10)
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#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
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#define RG_HDMITX_MHLCK_EN BIT(8)
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#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
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#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
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#define RG_HDMITX_SER_BIST_TOG BIT(2)
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#define RG_HDMITX_SER_DIN_TOG BIT(1)
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#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
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#define HDMI_CON4 0x10
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#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
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#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
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#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
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#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
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#define PRD_IBIAS_CLK_SHIFT 24
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#define PRD_IBIAS_D2_SHIFT 16
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#define PRD_IBIAS_D1_SHIFT 8
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#define PRD_IBIAS_D0_SHIFT 0
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#define HDMI_CON5 0x14
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#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
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#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
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#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
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#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
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#define DRV_IBIAS_CLK_SHIFT 24
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#define DRV_IBIAS_D2_SHIFT 16
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#define DRV_IBIAS_D1_SHIFT 8
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#define DRV_IBIAS_D0_SHIFT 0
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#define HDMI_CON6 0x18
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#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
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#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
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#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
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#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
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#define DRV_IMP_CLK_SHIFT 24
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#define DRV_IMP_D2_SHIFT 16
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#define DRV_IMP_D1_SHIFT 8
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#define DRV_IMP_D0_SHIFT 0
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#define HDMI_CON7 0x1c
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#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
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#define RG_HDMITX_SER_DIN (0x3ff << 16)
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#define RG_HDMITX_CHLDC_TST (0xf << 12)
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#define RG_HDMITX_CHLCK_TST (0xf << 8)
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#define RG_HDMITX_RESERVE (0xff << 0)
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#define HDMI_CON8 0x20
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#define RGS_HDMITX_2T1_LEV (0xf << 16)
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#define RGS_HDMITX_2T1_EDG (0xf << 12)
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#define RGS_HDMITX_5T1_LEV (0xf << 8)
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#define RGS_HDMITX_5T1_EDG (0xf << 4)
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#define RGS_HDMITX_PLUG_TST BIT(0)
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static const u8 PREDIV[3][4] = {
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{0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
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{0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
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{0x1, 0x1, 0x1, 0x1} /* 148Mhz */
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};
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static const u8 TXDIV[3][4] = {
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{0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
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{0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
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{0x1, 0x0, 0x0, 0x0} /* 148Mhz */
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};
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static const u8 FBKSEL[3][4] = {
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{0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
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{0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
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{0x1, 0x0, 0x1, 0x1} /* 148Mhz */
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};
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static const u8 FBKDIV[3][4] = {
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{19, 24, 29, 19}, /* 27Mhz */
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{19, 24, 14, 19}, /* 74Mhz */
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{19, 24, 14, 19} /* 148Mhz */
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};
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static const u8 DIVEN[3][4] = {
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{0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
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{0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
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{0x2, 0x2, 0x2, 0x2} /* 148Mhz */
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};
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static const u8 HTPLLBP[3][4] = {
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{0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
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{0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
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{0xc, 0xf, 0xf, 0xc} /* 148Mhz */
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};
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static const u8 HTPLLBC[3][4] = {
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{0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
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{0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
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{0x2, 0x3, 0x3, 0x2} /* 148Mhz */
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};
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static const u8 HTPLLBR[3][4] = {
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{0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
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{0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
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{0x1, 0x2, 0x2, 0x1} /* 148Mhz */
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};
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static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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dev_dbg(hdmi_phy->dev, "%s\n", __func__);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
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usleep_range(100, 150);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
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usleep_range(100, 150);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
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return 0;
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}
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static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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dev_dbg(hdmi_phy->dev, "%s\n", __func__);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
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usleep_range(100, 150);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
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usleep_range(100, 150);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
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usleep_range(100, 150);
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}
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static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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hdmi_phy->pll_rate = rate;
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if (rate <= 74250000)
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*parent_rate = rate;
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else
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*parent_rate = rate / 2;
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return rate;
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}
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static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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unsigned int pre_div;
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unsigned int div;
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unsigned int pre_ibias;
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unsigned int hdmi_ibias;
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unsigned int imp_en;
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dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
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rate, parent_rate);
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if (rate <= 27000000) {
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pre_div = 0;
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div = 3;
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} else if (rate <= 74250000) {
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pre_div = 1;
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div = 2;
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} else {
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pre_div = 1;
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div = 1;
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}
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
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RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
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(div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
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RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
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(0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
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(0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
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(0x1 << PLL_BR_SHIFT),
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RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
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RG_HDMITX_PLL_BR);
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if (rate < 165000000) {
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
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RG_HDMITX_PRD_IMP_EN);
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pre_ibias = 0x3;
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imp_en = 0x0;
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hdmi_ibias = hdmi_phy->ibias;
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} else {
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
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RG_HDMITX_PRD_IMP_EN);
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pre_ibias = 0x6;
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imp_en = 0xf;
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hdmi_ibias = hdmi_phy->ibias_up;
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}
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
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(pre_ibias << PRD_IBIAS_CLK_SHIFT) |
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(pre_ibias << PRD_IBIAS_D2_SHIFT) |
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(pre_ibias << PRD_IBIAS_D1_SHIFT) |
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(pre_ibias << PRD_IBIAS_D0_SHIFT),
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RG_HDMITX_PRD_IBIAS_CLK |
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RG_HDMITX_PRD_IBIAS_D2 |
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RG_HDMITX_PRD_IBIAS_D1 |
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RG_HDMITX_PRD_IBIAS_D0);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
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(imp_en << DRV_IMP_EN_SHIFT),
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RG_HDMITX_DRV_IMP_EN);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
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(hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
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(hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
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(hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
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(hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
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RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
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RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
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mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
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(hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
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(hdmi_ibias << DRV_IBIAS_D0_SHIFT),
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RG_HDMITX_DRV_IBIAS_CLK |
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RG_HDMITX_DRV_IBIAS_D2 |
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RG_HDMITX_DRV_IBIAS_D1 |
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RG_HDMITX_DRV_IBIAS_D0);
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return 0;
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}
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static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
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return hdmi_phy->pll_rate;
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}
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static const struct clk_ops mtk_hdmi_phy_pll_ops = {
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.prepare = mtk_hdmi_pll_prepare,
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.unprepare = mtk_hdmi_pll_unprepare,
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.set_rate = mtk_hdmi_pll_set_rate,
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.round_rate = mtk_hdmi_pll_round_rate,
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.recalc_rate = mtk_hdmi_pll_recalc_rate,
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};
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static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
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RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
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RG_HDMITX_DRV_EN);
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usleep_range(100, 150);
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}
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static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
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{
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mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
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RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
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RG_HDMITX_SER_EN);
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}
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struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
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.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
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.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
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.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
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.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
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};
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MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
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MODULE_LICENSE("GPL v2");
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