02f2b30032
On the D3 and E3 platforms, the LVDS internal PLL supplies the pixel clock to the DU. This works automatically for LVDS outputs as the LVDS encoder is enabled through the bridge API, enabling the internal PLL and clock output. However, when using the DU DPAD output with the LVDS outputs turned off, the LVDS PLL needs to be controlled manually. Add an API to do so, to be called by the DU driver. The drivers/gpu/drm/rcar-du/ directory has to be treated as obj-y unconditionally, as the LVDS driver could be built-in while the DU driver is compiled as a module. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
28 lines
710 B
C
28 lines
710 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* rcar_lvds.h -- R-Car LVDS Encoder
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*
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* Copyright (C) 2013-2018 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#ifndef __RCAR_LVDS_H__
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#define __RCAR_LVDS_H__
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struct drm_bridge;
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#if IS_ENABLED(CONFIG_DRM_RCAR_LVDS)
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int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq);
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void rcar_lvds_clk_disable(struct drm_bridge *bridge);
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#else
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static inline int rcar_lvds_clk_enable(struct drm_bridge *bridge,
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unsigned long freq)
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{
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return -ENOSYS;
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}
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static inline void rcar_lvds_clk_disable(struct drm_bridge *bridge) { }
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#endif /* CONFIG_DRM_RCAR_LVDS */
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#endif /* __RCAR_LVDS_H__ */
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