d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*/
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#ifndef __ZX_HDMI_REGS_H__
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#define __ZX_HDMI_REGS_H__
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#define FUNC_SEL 0x000b
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#define FUNC_HDMI_EN BIT(0)
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#define CLKPWD 0x000d
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#define CLKPWD_PDIDCK BIT(2)
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#define P2T_CTRL 0x0066
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#define P2T_DC_PKT_EN BIT(7)
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#define L1_INTR_STAT 0x007e
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#define L1_INTR_STAT_INTR1 BIT(0)
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#define INTR1_STAT 0x008f
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#define INTR1_MASK 0x0095
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#define INTR1_MONITOR_DETECT (BIT(5) | BIT(6))
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#define ZX_DDC_ADDR 0x00ed
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#define ZX_DDC_SEGM 0x00ee
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#define ZX_DDC_OFFSET 0x00ef
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#define ZX_DDC_DIN_CNT1 0x00f0
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#define ZX_DDC_DIN_CNT2 0x00f1
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#define ZX_DDC_CMD 0x00f3
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#define DDC_CMD_MASK 0xf
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#define DDC_CMD_CLEAR_FIFO 0x9
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#define DDC_CMD_SEQUENTIAL_READ 0x2
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#define ZX_DDC_DATA 0x00f4
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#define ZX_DDC_DOUT_CNT 0x00f5
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#define DDC_DOUT_CNT_MASK 0x1f
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#define TEST_TXCTRL 0x00f7
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#define TEST_TXCTRL_HDMI_MODE BIT(1)
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#define HDMICTL4 0x0235
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#define TPI_HPD_RSEN 0x063b
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#define TPI_HPD_CONNECTION (BIT(1) | BIT(2))
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#define TPI_INFO_FSEL 0x06bf
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#define FSEL_AVI 0
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#define FSEL_GBD 1
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#define FSEL_AUDIO 2
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#define FSEL_SPD 3
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#define FSEL_MPEG 4
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#define FSEL_VSIF 5
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#define TPI_INFO_B0 0x06c0
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#define TPI_INFO_EN 0x06df
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#define TPI_INFO_TRANS_EN BIT(7)
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#define TPI_INFO_TRANS_RPT BIT(6)
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#define TPI_DDC_MASTER_EN 0x06f8
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#define HW_DDC_MASTER BIT(7)
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#define N_SVAL1 0xa03
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#define N_SVAL2 0xa04
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#define N_SVAL3 0xa05
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#define AUD_EN 0xa13
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#define AUD_IN_EN BIT(0)
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#define AUD_MODE 0xa14
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#define SPDIF_EN BIT(1)
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#define TPI_AUD_CONFIG 0xa62
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#define SPDIF_SAMPLE_SIZE_SHIFT 6
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#define SPDIF_SAMPLE_SIZE_MASK (0x3 << SPDIF_SAMPLE_SIZE_SHIFT)
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#define SPDIF_SAMPLE_SIZE_16BIT (0x1 << SPDIF_SAMPLE_SIZE_SHIFT)
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#define SPDIF_SAMPLE_SIZE_20BIT (0x2 << SPDIF_SAMPLE_SIZE_SHIFT)
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#define SPDIF_SAMPLE_SIZE_24BIT (0x3 << SPDIF_SAMPLE_SIZE_SHIFT)
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#define TPI_AUD_MUTE BIT(4)
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#endif /* __ZX_HDMI_REGS_H__ */
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