![Nick Bowler](/assets/img/avatar_default.png)
There are no reads in these functions, so if MMIO writes are posted, the writes in enable/disable may not have completed by the time these functions return. If the functions run from different CPUs, it's in theory possible for the writes to be interleaved, which would be disastrous for this driver. At the very least, we need an mmiowb() before releasing the lock, but since it seems desirable for the watchdog timer to be actually stopped or reset when these functions return, read the lock register to force the writes out. Signed-off-by: Nick Bowler <nbowler@elliptictech.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
391 lines
8.6 KiB
C
391 lines
8.6 KiB
C
/*
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* drivers/char/watchdog/sp805-wdt.c
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*
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* Watchdog driver for ARM SP805 watchdog module
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*
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* Copyright (C) 2010 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2 or later. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/device.h>
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#include <linux/resource.h>
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#include <linux/amba/bus.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/watchdog.h>
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/* default timeout in seconds */
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#define DEFAULT_TIMEOUT 60
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#define MODULE_NAME "sp805-wdt"
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/* watchdog register offsets and masks */
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#define WDTLOAD 0x000
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#define LOAD_MIN 0x00000001
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#define LOAD_MAX 0xFFFFFFFF
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#define WDTVALUE 0x004
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#define WDTCONTROL 0x008
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/* control register masks */
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#define INT_ENABLE (1 << 0)
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#define RESET_ENABLE (1 << 1)
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#define WDTINTCLR 0x00C
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#define WDTRIS 0x010
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#define WDTMIS 0x014
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#define INT_MASK (1 << 0)
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#define WDTLOCK 0xC00
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#define UNLOCK 0x1ACCE551
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#define LOCK 0x00000001
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/**
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* struct sp805_wdt: sp805 wdt device structure
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*
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* lock: spin lock protecting dev structure and io access
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* base: base address of wdt
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* clk: clock structure of wdt
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* dev: amba device structure of wdt
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* status: current status of wdt
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* load_val: load value to be set for current timeout
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* timeout: current programmed timeout
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*/
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struct sp805_wdt {
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spinlock_t lock;
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void __iomem *base;
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struct clk *clk;
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struct amba_device *adev;
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unsigned long status;
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#define WDT_BUSY 0
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#define WDT_CAN_BE_CLOSED 1
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unsigned int load_val;
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unsigned int timeout;
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};
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/* local variables */
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static struct sp805_wdt *wdt;
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static int nowayout = WATCHDOG_NOWAYOUT;
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/* This routine finds load value that will reset system in required timout */
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static void wdt_setload(unsigned int timeout)
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{
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u64 load, rate;
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rate = clk_get_rate(wdt->clk);
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/*
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* sp805 runs counter with given value twice, after the end of first
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* counter it gives an interrupt and then starts counter again. If
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* interrupt already occurred then it resets the system. This is why
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* load is half of what should be required.
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*/
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load = div_u64(rate, 2) * timeout - 1;
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load = (load > LOAD_MAX) ? LOAD_MAX : load;
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load = (load < LOAD_MIN) ? LOAD_MIN : load;
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spin_lock(&wdt->lock);
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wdt->load_val = load;
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/* roundup timeout to closest positive integer value */
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wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
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spin_unlock(&wdt->lock);
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}
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/* returns number of seconds left for reset to occur */
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static u32 wdt_timeleft(void)
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{
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u64 load, rate;
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rate = clk_get_rate(wdt->clk);
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spin_lock(&wdt->lock);
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load = readl(wdt->base + WDTVALUE);
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/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
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if (!(readl(wdt->base + WDTRIS) & INT_MASK))
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load += wdt->load_val + 1;
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spin_unlock(&wdt->lock);
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return div_u64(load, rate);
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}
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/* enables watchdog timers reset */
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static void wdt_enable(void)
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{
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spin_lock(&wdt->lock);
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writel(UNLOCK, wdt->base + WDTLOCK);
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writel(wdt->load_val, wdt->base + WDTLOAD);
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writel(INT_MASK, wdt->base + WDTINTCLR);
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writel(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
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writel(LOCK, wdt->base + WDTLOCK);
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/* Flush posted writes. */
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readl(wdt->base + WDTLOCK);
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spin_unlock(&wdt->lock);
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}
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/* disables watchdog timers reset */
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static void wdt_disable(void)
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{
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spin_lock(&wdt->lock);
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writel(UNLOCK, wdt->base + WDTLOCK);
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writel(0, wdt->base + WDTCONTROL);
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writel(LOCK, wdt->base + WDTLOCK);
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/* Flush posted writes. */
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readl(wdt->base + WDTLOCK);
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spin_unlock(&wdt->lock);
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}
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static ssize_t sp805_wdt_write(struct file *file, const char *data,
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size_t len, loff_t *ppos)
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{
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if (len) {
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if (!nowayout) {
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size_t i;
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clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
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for (i = 0; i != len; i++) {
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char c;
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if (get_user(c, data + i))
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return -EFAULT;
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/* Check for Magic Close character */
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if (c == 'V') {
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set_bit(WDT_CAN_BE_CLOSED,
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&wdt->status);
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break;
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}
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}
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}
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wdt_enable();
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}
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return len;
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}
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static const struct watchdog_info ident = {
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.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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.identity = MODULE_NAME,
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};
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static long sp805_wdt_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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int ret = -ENOTTY;
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unsigned int timeout;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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ret = copy_to_user((struct watchdog_info *)arg, &ident,
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sizeof(ident)) ? -EFAULT : 0;
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break;
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case WDIOC_GETSTATUS:
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ret = put_user(0, (int *)arg);
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break;
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case WDIOC_KEEPALIVE:
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wdt_enable();
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ret = 0;
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break;
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case WDIOC_SETTIMEOUT:
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ret = get_user(timeout, (unsigned int *)arg);
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if (ret)
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break;
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wdt_setload(timeout);
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wdt_enable();
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/* Fall through */
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case WDIOC_GETTIMEOUT:
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ret = put_user(wdt->timeout, (unsigned int *)arg);
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break;
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case WDIOC_GETTIMELEFT:
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ret = put_user(wdt_timeleft(), (unsigned int *)arg);
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break;
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}
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return ret;
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}
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static int sp805_wdt_open(struct inode *inode, struct file *file)
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{
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int ret = 0;
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if (test_and_set_bit(WDT_BUSY, &wdt->status))
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return -EBUSY;
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ret = clk_enable(wdt->clk);
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if (ret) {
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dev_err(&wdt->adev->dev, "clock enable fail");
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goto err;
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}
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wdt_enable();
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/* can not be closed, once enabled */
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clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
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return nonseekable_open(inode, file);
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err:
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clear_bit(WDT_BUSY, &wdt->status);
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return ret;
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}
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static int sp805_wdt_release(struct inode *inode, struct file *file)
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{
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if (!test_bit(WDT_CAN_BE_CLOSED, &wdt->status)) {
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clear_bit(WDT_BUSY, &wdt->status);
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dev_warn(&wdt->adev->dev, "Device closed unexpectedly\n");
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return 0;
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}
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wdt_disable();
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clk_disable(wdt->clk);
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clear_bit(WDT_BUSY, &wdt->status);
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return 0;
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}
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static const struct file_operations sp805_wdt_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = sp805_wdt_write,
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.unlocked_ioctl = sp805_wdt_ioctl,
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.open = sp805_wdt_open,
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.release = sp805_wdt_release,
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};
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static struct miscdevice sp805_wdt_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &sp805_wdt_fops,
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};
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static int __devinit
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sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
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{
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int ret = 0;
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if (!request_mem_region(adev->res.start, resource_size(&adev->res),
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"sp805_wdt")) {
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dev_warn(&adev->dev, "Failed to get memory region resource\n");
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ret = -ENOENT;
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goto err;
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}
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wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
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if (!wdt) {
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dev_warn(&adev->dev, "Kzalloc failed\n");
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ret = -ENOMEM;
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goto err_kzalloc;
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}
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wdt->clk = clk_get(&adev->dev, NULL);
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if (IS_ERR(wdt->clk)) {
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dev_warn(&adev->dev, "Clock not found\n");
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ret = PTR_ERR(wdt->clk);
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goto err_clk_get;
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}
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wdt->base = ioremap(adev->res.start, resource_size(&adev->res));
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if (!wdt->base) {
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ret = -ENOMEM;
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dev_warn(&adev->dev, "ioremap fail\n");
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goto err_ioremap;
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}
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wdt->adev = adev;
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spin_lock_init(&wdt->lock);
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wdt_setload(DEFAULT_TIMEOUT);
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ret = misc_register(&sp805_wdt_miscdev);
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if (ret < 0) {
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dev_warn(&adev->dev, "cannot register misc device\n");
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goto err_misc_register;
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}
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dev_info(&adev->dev, "registration successful\n");
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return 0;
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err_misc_register:
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iounmap(wdt->base);
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err_ioremap:
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clk_put(wdt->clk);
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err_clk_get:
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kfree(wdt);
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wdt = NULL;
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err_kzalloc:
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release_mem_region(adev->res.start, resource_size(&adev->res));
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err:
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dev_err(&adev->dev, "Probe Failed!!!\n");
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return ret;
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}
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static int __devexit sp805_wdt_remove(struct amba_device *adev)
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{
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misc_deregister(&sp805_wdt_miscdev);
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iounmap(wdt->base);
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clk_put(wdt->clk);
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kfree(wdt);
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release_mem_region(adev->res.start, resource_size(&adev->res));
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return 0;
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}
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static struct amba_id sp805_wdt_ids[] __initdata = {
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{
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.id = 0x00141805,
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.mask = 0x00ffffff,
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},
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{ 0, 0 },
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};
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static struct amba_driver sp805_wdt_driver = {
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.drv = {
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.name = MODULE_NAME,
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},
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.id_table = sp805_wdt_ids,
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.probe = sp805_wdt_probe,
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.remove = __devexit_p(sp805_wdt_remove),
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};
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static int __init sp805_wdt_init(void)
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{
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return amba_driver_register(&sp805_wdt_driver);
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}
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module_init(sp805_wdt_init);
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static void __exit sp805_wdt_exit(void)
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{
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amba_driver_unregister(&sp805_wdt_driver);
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}
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module_exit(sp805_wdt_exit);
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module_param(nowayout, int, 0);
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MODULE_PARM_DESC(nowayout,
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"Set to 1 to keep watchdog running after device release");
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MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
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MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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