![Scott Wood](/assets/img/avatar_default.png)
Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Diana Craciun <diana.craciun@freescale.com>
538 lines
14 KiB
Plaintext
538 lines
14 KiB
Plaintext
/*
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* P4080/P4040 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&lbc {
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compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
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interrupts = <25 2 0 0>;
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#address-cells = <2>;
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#size-cells = <1>;
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};
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/* controller at 0x200000 */
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&pci0 {
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compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 1 15>;
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 1 15>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 40 1 0 0
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0000 0 0 2 &mpic 1 1 0 0
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0000 0 0 3 &mpic 2 1 0 0
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0000 0 0 4 &mpic 3 1 0 0
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>;
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};
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};
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/* controller at 0x201000 */
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&pci1 {
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compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 1 14>;
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 1 14>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 41 1 0 0
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0000 0 0 2 &mpic 5 1 0 0
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0000 0 0 3 &mpic 6 1 0 0
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0000 0 0 4 &mpic 7 1 0 0
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>;
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};
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};
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/* controller at 0x202000 */
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&pci2 {
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compatible = "fsl,p4080-pcie", "fsl,qoriq-pcie-v2.1";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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clock-frequency = <33333333>;
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interrupts = <16 2 1 13>;
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
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pcie@0 {
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reg = <0 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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interrupts = <16 2 1 13>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 42 1 0 0
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0000 0 0 2 &mpic 9 1 0 0
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0000 0 0 3 &mpic 10 1 0 0
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0000 0 0 4 &mpic 11 1 0 0
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>;
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};
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};
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&rio {
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compatible = "fsl,srio";
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interrupts = <16 2 1 11>;
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#address-cells = <2>;
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#size-cells = <2>;
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fsl,srio-rmu-handle = <&rmu>;
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fsl,iommu-parent = <&pamu0>;
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ranges;
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port1 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <1>;
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fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
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};
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port2 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <2>;
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fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
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};
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};
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&dcsr {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,dcsr", "simple-bus";
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dcsr-epu@0 {
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compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
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interrupts = <52 2 0 0
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84 2 0 0
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85 2 0 0>;
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reg = <0x0 0x1000>;
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};
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dcsr-npc {
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compatible = "fsl,dcsr-npc";
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reg = <0x1000 0x1000 0x1000000 0x8000>;
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};
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dcsr-nxc@2000 {
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compatible = "fsl,dcsr-nxc";
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reg = <0x2000 0x1000>;
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};
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dcsr-corenet {
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compatible = "fsl,dcsr-corenet";
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reg = <0x8000 0x1000 0xB0000 0x1000>;
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};
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dcsr-dpaa@9000 {
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compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
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reg = <0x9000 0x1000>;
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};
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dcsr-ocn@11000 {
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compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
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reg = <0x11000 0x1000>;
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};
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dcsr-ddr@12000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr1>;
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reg = <0x12000 0x1000>;
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};
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dcsr-ddr@13000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr2>;
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reg = <0x13000 0x1000>;
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};
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dcsr-nal@18000 {
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compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
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reg = <0x18000 0x1000>;
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};
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dcsr-rcpm@22000 {
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compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
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reg = <0x22000 0x1000>;
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};
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dcsr-cpu-sb-proxy@40000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu0>;
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reg = <0x40000 0x1000>;
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};
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dcsr-cpu-sb-proxy@41000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu1>;
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reg = <0x41000 0x1000>;
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};
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dcsr-cpu-sb-proxy@42000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu2>;
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reg = <0x42000 0x1000>;
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};
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dcsr-cpu-sb-proxy@43000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu3>;
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reg = <0x43000 0x1000>;
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};
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dcsr-cpu-sb-proxy@44000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu4>;
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reg = <0x44000 0x1000>;
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};
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dcsr-cpu-sb-proxy@45000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu5>;
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reg = <0x45000 0x1000>;
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};
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dcsr-cpu-sb-proxy@46000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu6>;
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reg = <0x46000 0x1000>;
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};
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dcsr-cpu-sb-proxy@47000 {
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compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu7>;
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reg = <0x47000 0x1000>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 29>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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ddr1: memory-controller@8000 {
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compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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ddr2: memory-controller@9000 {
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compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
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reg = <0x9000 0x1000>;
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interrupts = <16 2 1 22>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,p4080-l3-cache-controller", "cache";
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reg = <0x10000 0x1000
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0x11000 0x1000>;
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interrupts = <16 2 1 27
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16 2 1 26>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x5000>; /* for compatibility with older PAMU drivers */
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ranges = <0 0x20000 0x5000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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fsl,portid-mapping = <0x00f80000>;
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pamu0: pamu@0 {
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reg = <0 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu1: pamu@1000 {
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reg = <0x1000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu2: pamu@2000 {
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reg = <0x2000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu3: pamu@3000 {
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reg = <0x3000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu4: pamu@4000 {
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reg = <0x4000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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};
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/include/ "qoriq-rmu-0.dtsi"
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rmu@d3000 {
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x540>; /* RMULIODNR */
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};
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/include/ "qoriq-mpic.dtsi"
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guts: global-utilities@e0000 {
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compatible = "fsl,qoriq-device-config-1.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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#sleep-cells = <1>;
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fsl,liodn-bits = <12>;
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};
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pins: global-utilities@e0e00 {
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compatible = "fsl,qoriq-pin-control-1.0";
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reg = <0xe0e00 0x200>;
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#sleep-cells = <2>;
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};
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clockgen: global-utilities@e1000 {
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compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
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ranges = <0x0 0xe1000 0x1000>;
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reg = <0xe1000 0x1000>;
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clock-frequency = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fsl,qoriq-sysclk-1.0";
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clock-output-names = "sysclk";
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};
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pll0: pll0@800 {
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#clock-cells = <1>;
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reg = <0x800 0x4>;
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compatible = "fsl,qoriq-core-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "pll0", "pll0-div2";
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};
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pll1: pll1@820 {
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#clock-cells = <1>;
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reg = <0x820 0x4>;
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compatible = "fsl,qoriq-core-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "pll1", "pll1-div2";
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};
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pll2: pll2@840 {
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#clock-cells = <1>;
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reg = <0x840 0x4>;
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compatible = "fsl,qoriq-core-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "pll2", "pll2-div2";
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};
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pll3: pll3@860 {
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#clock-cells = <1>;
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reg = <0x860 0x4>;
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compatible = "fsl,qoriq-core-pll-1.0";
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clocks = <&sysclk>;
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clock-output-names = "pll3", "pll3-div2";
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};
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mux0: mux0@0 {
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#clock-cells = <0>;
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reg = <0x0 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux0";
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};
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mux1: mux1@20 {
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#clock-cells = <0>;
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reg = <0x20 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux1";
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};
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mux2: mux2@40 {
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#clock-cells = <0>;
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reg = <0x40 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux2";
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};
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mux3: mux3@60 {
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#clock-cells = <0>;
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reg = <0x60 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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clock-output-names = "cmux3";
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};
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mux4: mux4@80 {
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#clock-cells = <0>;
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reg = <0x80 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
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clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
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clock-output-names = "cmux4";
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};
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mux5: mux5@a0 {
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#clock-cells = <0>;
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reg = <0xa0 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
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clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
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clock-output-names = "cmux5";
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};
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mux6: mux6@c0 {
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#clock-cells = <0>;
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reg = <0xc0 0x4>;
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compatible = "fsl,qoriq-core-mux-1.0";
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clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
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clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
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clock-output-names = "cmux6";
|
|
};
|
|
|
|
mux7: mux7@e0 {
|
|
#clock-cells = <0>;
|
|
reg = <0xe0 0x4>;
|
|
compatible = "fsl,qoriq-core-mux-1.0";
|
|
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
|
|
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
|
|
clock-output-names = "cmux7";
|
|
};
|
|
};
|
|
|
|
rcpm: global-utilities@e2000 {
|
|
compatible = "fsl,qoriq-rcpm-1.0";
|
|
reg = <0xe2000 0x1000>;
|
|
#sleep-cells = <1>;
|
|
};
|
|
|
|
sfp: sfp@e8000 {
|
|
compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
|
|
reg = <0xe8000 0x1000>;
|
|
};
|
|
|
|
serdes: serdes@ea000 {
|
|
compatible = "fsl,p4080-serdes";
|
|
reg = <0xea000 0x1000>;
|
|
};
|
|
|
|
/include/ "qoriq-dma-0.dtsi"
|
|
dma@100300 {
|
|
fsl,iommu-parent = <&pamu0>;
|
|
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
|
};
|
|
|
|
/include/ "qoriq-dma-1.dtsi"
|
|
dma@101300 {
|
|
fsl,iommu-parent = <&pamu0>;
|
|
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
|
};
|
|
|
|
/include/ "qoriq-espi-0.dtsi"
|
|
spi@110000 {
|
|
fsl,espi-num-chipselects = <4>;
|
|
};
|
|
|
|
/include/ "qoriq-esdhc-0.dtsi"
|
|
sdhc@114000 {
|
|
fsl,iommu-parent = <&pamu1>;
|
|
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
|
voltage-ranges = <3300 3300>;
|
|
sdhci,auto-cmd12;
|
|
};
|
|
|
|
/include/ "qoriq-i2c-0.dtsi"
|
|
/include/ "qoriq-i2c-1.dtsi"
|
|
/include/ "qoriq-duart-0.dtsi"
|
|
/include/ "qoriq-duart-1.dtsi"
|
|
/include/ "qoriq-gpio-0.dtsi"
|
|
/include/ "qoriq-usb2-mph-0.dtsi"
|
|
usb@210000 {
|
|
compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
|
|
fsl,iommu-parent = <&pamu1>;
|
|
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
|
port0;
|
|
};
|
|
/include/ "qoriq-usb2-dr-0.dtsi"
|
|
usb@211000 {
|
|
compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
|
|
fsl,iommu-parent = <&pamu1>;
|
|
fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
|
|
};
|
|
/include/ "qoriq-sec4.0-0.dtsi"
|
|
crypto: crypto@300000 {
|
|
fsl,iommu-parent = <&pamu1>;
|
|
};
|
|
};
|