![Shengzhou Liu](/assets/img/avatar_default.png)
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power Architecture processor cores with high-performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and mil/aerospace applications. The T2080 SoC includes the following function and features: - Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 T2081 is a reduced personality of T2080 with following difference: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [scottwood@freescale.com: added fsl,qoriq-pci-v3.0 for U-Boot compat] Signed-off-by: Scott Wood <scottwood@freescale.com>
100 lines
2.9 KiB
Plaintext
100 lines
2.9 KiB
Plaintext
/*
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* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/include/ "e6500_power_isa.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ccsr = &soc;
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dcsr = &dcsr;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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crypto = &crypto;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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pci3 = &pci3;
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usb0 = &usb0;
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usb1 = &usb1;
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dma0 = &dma0;
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dma1 = &dma1;
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dma2 = &dma2;
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sdhc = &sdhc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,e6500@0 {
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device_type = "cpu";
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reg = <0 1>;
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clocks = <&mux0>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu1: PowerPC,e6500@2 {
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device_type = "cpu";
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reg = <2 3>;
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clocks = <&mux0>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu2: PowerPC,e6500@4 {
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device_type = "cpu";
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reg = <4 5>;
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clocks = <&mux0>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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cpu3: PowerPC,e6500@6 {
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device_type = "cpu";
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reg = <6 7>;
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clocks = <&mux0>;
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next-level-cache = <&L2_1>;
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fsl,portid-mapping = <0x80000000>;
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};
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};
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};
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