![Gregory CLEMENT](/assets/img/avatar_default.png)
On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
583 lines
14 KiB
C
583 lines
14 KiB
C
/*
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* omap-rng.c - RNG driver for TI OMAP CPU family
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* Mostly based on original driver:
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/random.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/hw_random.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#define RNG_REG_STATUS_RDY (1 << 0)
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#define RNG_REG_INTACK_RDY_MASK (1 << 0)
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#define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
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#define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
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#define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
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#define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
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#define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
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#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
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#define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
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#define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
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#define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
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#define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
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#define RNG_CONTROL_STARTUP_CYCLES 0xff
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#define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
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#define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
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#define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
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#define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
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#define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
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#define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
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#define RNG_ALARM_THRESHOLD 0xff
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#define RNG_SHUTDOWN_THRESHOLD 0x4
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#define RNG_REG_FROENABLE_MASK 0xffffff
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#define RNG_REG_FRODETUNE_MASK 0xffffff
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#define OMAP2_RNG_OUTPUT_SIZE 0x4
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#define OMAP4_RNG_OUTPUT_SIZE 0x8
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#define EIP76_RNG_OUTPUT_SIZE 0x10
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enum {
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RNG_OUTPUT_0_REG = 0,
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RNG_OUTPUT_1_REG,
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RNG_OUTPUT_2_REG,
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RNG_OUTPUT_3_REG,
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RNG_STATUS_REG,
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RNG_INTMASK_REG,
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RNG_INTACK_REG,
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RNG_CONTROL_REG,
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RNG_CONFIG_REG,
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RNG_ALARMCNT_REG,
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RNG_FROENABLE_REG,
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RNG_FRODETUNE_REG,
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RNG_ALARMMASK_REG,
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RNG_ALARMSTOP_REG,
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RNG_REV_REG,
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RNG_SYSCONFIG_REG,
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};
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static const u16 reg_map_omap2[] = {
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[RNG_OUTPUT_0_REG] = 0x0,
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[RNG_STATUS_REG] = 0x4,
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[RNG_CONFIG_REG] = 0x28,
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[RNG_REV_REG] = 0x3c,
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[RNG_SYSCONFIG_REG] = 0x40,
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};
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static const u16 reg_map_omap4[] = {
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[RNG_OUTPUT_0_REG] = 0x0,
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[RNG_OUTPUT_1_REG] = 0x4,
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[RNG_STATUS_REG] = 0x8,
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[RNG_INTMASK_REG] = 0xc,
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[RNG_INTACK_REG] = 0x10,
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[RNG_CONTROL_REG] = 0x14,
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[RNG_CONFIG_REG] = 0x18,
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[RNG_ALARMCNT_REG] = 0x1c,
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[RNG_FROENABLE_REG] = 0x20,
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[RNG_FRODETUNE_REG] = 0x24,
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[RNG_ALARMMASK_REG] = 0x28,
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[RNG_ALARMSTOP_REG] = 0x2c,
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[RNG_REV_REG] = 0x1FE0,
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[RNG_SYSCONFIG_REG] = 0x1FE4,
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};
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static const u16 reg_map_eip76[] = {
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[RNG_OUTPUT_0_REG] = 0x0,
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[RNG_OUTPUT_1_REG] = 0x4,
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[RNG_OUTPUT_2_REG] = 0x8,
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[RNG_OUTPUT_3_REG] = 0xc,
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[RNG_STATUS_REG] = 0x10,
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[RNG_INTACK_REG] = 0x10,
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[RNG_CONTROL_REG] = 0x14,
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[RNG_CONFIG_REG] = 0x18,
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[RNG_ALARMCNT_REG] = 0x1c,
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[RNG_FROENABLE_REG] = 0x20,
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[RNG_FRODETUNE_REG] = 0x24,
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[RNG_ALARMMASK_REG] = 0x28,
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[RNG_ALARMSTOP_REG] = 0x2c,
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[RNG_REV_REG] = 0x7c,
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};
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struct omap_rng_dev;
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/**
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* struct omap_rng_pdata - RNG IP block-specific data
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* @regs: Pointer to the register offsets structure.
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* @data_size: No. of bytes in RNG output.
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* @data_present: Callback to determine if data is available.
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* @init: Callback for IP specific initialization sequence.
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* @cleanup: Callback for IP specific cleanup sequence.
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*/
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struct omap_rng_pdata {
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u16 *regs;
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u32 data_size;
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u32 (*data_present)(struct omap_rng_dev *priv);
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int (*init)(struct omap_rng_dev *priv);
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void (*cleanup)(struct omap_rng_dev *priv);
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};
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struct omap_rng_dev {
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void __iomem *base;
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struct device *dev;
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const struct omap_rng_pdata *pdata;
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struct hwrng rng;
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struct clk *clk;
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struct clk *clk_reg;
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};
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static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
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{
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return __raw_readl(priv->base + priv->pdata->regs[reg]);
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}
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static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
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u32 val)
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{
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__raw_writel(val, priv->base + priv->pdata->regs[reg]);
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}
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static int omap_rng_do_read(struct hwrng *rng, void *data, size_t max,
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bool wait)
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{
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struct omap_rng_dev *priv;
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int i, present;
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priv = (struct omap_rng_dev *)rng->priv;
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if (max < priv->pdata->data_size)
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return 0;
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for (i = 0; i < 20; i++) {
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present = priv->pdata->data_present(priv);
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if (present || !wait)
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break;
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udelay(10);
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}
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if (!present)
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return 0;
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memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG],
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priv->pdata->data_size);
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if (priv->pdata->regs[RNG_INTACK_REG])
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omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
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return priv->pdata->data_size;
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}
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static int omap_rng_init(struct hwrng *rng)
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{
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struct omap_rng_dev *priv;
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priv = (struct omap_rng_dev *)rng->priv;
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return priv->pdata->init(priv);
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}
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static void omap_rng_cleanup(struct hwrng *rng)
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{
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struct omap_rng_dev *priv;
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priv = (struct omap_rng_dev *)rng->priv;
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priv->pdata->cleanup(priv);
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}
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static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
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{
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return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
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}
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static int omap2_rng_init(struct omap_rng_dev *priv)
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{
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omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
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return 0;
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}
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static void omap2_rng_cleanup(struct omap_rng_dev *priv)
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{
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omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
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}
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static struct omap_rng_pdata omap2_rng_pdata = {
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.regs = (u16 *)reg_map_omap2,
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.data_size = OMAP2_RNG_OUTPUT_SIZE,
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.data_present = omap2_rng_data_present,
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.init = omap2_rng_init,
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.cleanup = omap2_rng_cleanup,
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};
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#if defined(CONFIG_OF)
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static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
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{
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return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
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}
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static int eip76_rng_init(struct omap_rng_dev *priv)
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{
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u32 val;
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/* Return if RNG is already running. */
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if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
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return 0;
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/* Number of 512 bit blocks of raw Noise Source output data that must
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* be processed by either the Conditioning Function or the
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* SP 800-90 DRBG ‘BC_DF’ functionality to yield a ‘full entropy’
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* output value.
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*/
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val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
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/* Number of FRO samples that are XOR-ed together into one bit to be
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* shifted into the main shift register
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*/
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val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
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omap_rng_write(priv, RNG_CONFIG_REG, val);
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/* Enable all available FROs */
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omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
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omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
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/* Enable TRNG */
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val = RNG_CONTROL_ENABLE_TRNG_MASK;
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omap_rng_write(priv, RNG_CONTROL_REG, val);
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return 0;
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}
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static int omap4_rng_init(struct omap_rng_dev *priv)
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{
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u32 val;
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/* Return if RNG is already running. */
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if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
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return 0;
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val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
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val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
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omap_rng_write(priv, RNG_CONFIG_REG, val);
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omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
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omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
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val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
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val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
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omap_rng_write(priv, RNG_ALARMCNT_REG, val);
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val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
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val |= RNG_CONTROL_ENABLE_TRNG_MASK;
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omap_rng_write(priv, RNG_CONTROL_REG, val);
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return 0;
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}
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static void omap4_rng_cleanup(struct omap_rng_dev *priv)
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{
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int val;
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val = omap_rng_read(priv, RNG_CONTROL_REG);
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val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
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omap_rng_write(priv, RNG_CONTROL_REG, val);
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}
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static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
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{
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struct omap_rng_dev *priv = dev_id;
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u32 fro_detune, fro_enable;
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/*
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* Interrupt raised by a fro shutdown threshold, do the following:
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* 1. Clear the alarm events.
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* 2. De tune the FROs which are shutdown.
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* 3. Re enable the shutdown FROs.
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*/
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omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
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omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
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fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
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fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
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fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
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fro_enable = RNG_REG_FROENABLE_MASK;
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omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
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omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
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omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
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return IRQ_HANDLED;
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}
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static struct omap_rng_pdata omap4_rng_pdata = {
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.regs = (u16 *)reg_map_omap4,
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.data_size = OMAP4_RNG_OUTPUT_SIZE,
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.data_present = omap4_rng_data_present,
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.init = omap4_rng_init,
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.cleanup = omap4_rng_cleanup,
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};
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static struct omap_rng_pdata eip76_rng_pdata = {
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.regs = (u16 *)reg_map_eip76,
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.data_size = EIP76_RNG_OUTPUT_SIZE,
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.data_present = omap4_rng_data_present,
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.init = eip76_rng_init,
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.cleanup = omap4_rng_cleanup,
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};
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static const struct of_device_id omap_rng_of_match[] = {
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{
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.compatible = "ti,omap2-rng",
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.data = &omap2_rng_pdata,
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},
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{
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.compatible = "ti,omap4-rng",
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.data = &omap4_rng_pdata,
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},
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{
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.compatible = "inside-secure,safexcel-eip76",
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.data = &eip76_rng_pdata,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, omap_rng_of_match);
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static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
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struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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int irq, err;
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match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
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if (!match) {
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dev_err(dev, "no compatible OF match\n");
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return -EINVAL;
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}
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priv->pdata = match->data;
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if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") ||
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of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) {
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "%s: error getting IRQ resource - %d\n",
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__func__, irq);
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return irq;
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}
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err = devm_request_irq(dev, irq, omap4_rng_irq,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (err) {
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dev_err(dev, "unable to request irq %d, err = %d\n",
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irq, err);
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return err;
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}
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/*
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* On OMAP4, enabling the shutdown_oflo interrupt is
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* done in the interrupt mask register. There is no
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* such register on EIP76, and it's enabled by the
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* same bit in the control register
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*/
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if (priv->pdata->regs[RNG_INTMASK_REG])
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omap_rng_write(priv, RNG_INTMASK_REG,
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RNG_SHUTDOWN_OFLO_MASK);
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else
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omap_rng_write(priv, RNG_CONTROL_REG,
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RNG_SHUTDOWN_OFLO_MASK);
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}
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return 0;
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}
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#else
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static int of_get_omap_rng_device_details(struct omap_rng_dev *omap_rng,
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struct platform_device *pdev)
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{
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return -EINVAL;
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}
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#endif
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static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
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{
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/* Only OMAP2/3 can be non-DT */
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omap_rng->pdata = &omap2_rng_pdata;
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return 0;
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}
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static int omap_rng_probe(struct platform_device *pdev)
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{
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struct omap_rng_dev *priv;
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struct resource *res;
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struct device *dev = &pdev->dev;
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int ret;
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priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->rng.read = omap_rng_do_read;
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priv->rng.init = omap_rng_init;
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priv->rng.cleanup = omap_rng_cleanup;
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priv->rng.priv = (unsigned long)priv;
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platform_set_drvdata(pdev, priv);
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priv->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base)) {
|
||
ret = PTR_ERR(priv->base);
|
||
goto err_ioremap;
|
||
}
|
||
|
||
priv->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
|
||
if (!priv->rng.name) {
|
||
ret = -ENOMEM;
|
||
goto err_ioremap;
|
||
}
|
||
|
||
pm_runtime_enable(&pdev->dev);
|
||
ret = pm_runtime_get_sync(&pdev->dev);
|
||
if (ret < 0) {
|
||
dev_err(&pdev->dev, "Failed to runtime_get device: %d\n", ret);
|
||
pm_runtime_put_noidle(&pdev->dev);
|
||
goto err_ioremap;
|
||
}
|
||
|
||
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
||
if (IS_ERR(priv->clk) && PTR_ERR(priv->clk) == -EPROBE_DEFER)
|
||
return -EPROBE_DEFER;
|
||
if (!IS_ERR(priv->clk)) {
|
||
ret = clk_prepare_enable(priv->clk);
|
||
if (ret) {
|
||
dev_err(&pdev->dev,
|
||
"Unable to enable the clk: %d\n", ret);
|
||
goto err_register;
|
||
}
|
||
}
|
||
|
||
priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
|
||
if (IS_ERR(priv->clk_reg) && PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
|
||
return -EPROBE_DEFER;
|
||
if (!IS_ERR(priv->clk_reg)) {
|
||
ret = clk_prepare_enable(priv->clk_reg);
|
||
if (ret) {
|
||
dev_err(&pdev->dev,
|
||
"Unable to enable the register clk: %d\n",
|
||
ret);
|
||
goto err_register;
|
||
}
|
||
}
|
||
|
||
ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
|
||
get_omap_rng_device_details(priv);
|
||
if (ret)
|
||
goto err_register;
|
||
|
||
ret = hwrng_register(&priv->rng);
|
||
if (ret)
|
||
goto err_register;
|
||
|
||
dev_info(&pdev->dev, "Random Number Generator ver. %02x\n",
|
||
omap_rng_read(priv, RNG_REV_REG));
|
||
|
||
return 0;
|
||
|
||
err_register:
|
||
priv->base = NULL;
|
||
pm_runtime_put_sync(&pdev->dev);
|
||
pm_runtime_disable(&pdev->dev);
|
||
|
||
clk_disable_unprepare(priv->clk_reg);
|
||
clk_disable_unprepare(priv->clk);
|
||
err_ioremap:
|
||
dev_err(dev, "initialization failed.\n");
|
||
return ret;
|
||
}
|
||
|
||
static int omap_rng_remove(struct platform_device *pdev)
|
||
{
|
||
struct omap_rng_dev *priv = platform_get_drvdata(pdev);
|
||
|
||
hwrng_unregister(&priv->rng);
|
||
|
||
priv->pdata->cleanup(priv);
|
||
|
||
pm_runtime_put_sync(&pdev->dev);
|
||
pm_runtime_disable(&pdev->dev);
|
||
|
||
clk_disable_unprepare(priv->clk);
|
||
clk_disable_unprepare(priv->clk_reg);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int __maybe_unused omap_rng_suspend(struct device *dev)
|
||
{
|
||
struct omap_rng_dev *priv = dev_get_drvdata(dev);
|
||
|
||
priv->pdata->cleanup(priv);
|
||
pm_runtime_put_sync(dev);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int __maybe_unused omap_rng_resume(struct device *dev)
|
||
{
|
||
struct omap_rng_dev *priv = dev_get_drvdata(dev);
|
||
int ret;
|
||
|
||
ret = pm_runtime_get_sync(dev);
|
||
if (ret < 0) {
|
||
dev_err(dev, "Failed to runtime_get device: %d\n", ret);
|
||
pm_runtime_put_noidle(dev);
|
||
return ret;
|
||
}
|
||
|
||
priv->pdata->init(priv);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
|
||
|
||
static struct platform_driver omap_rng_driver = {
|
||
.driver = {
|
||
.name = "omap_rng",
|
||
.pm = &omap_rng_pm,
|
||
.of_match_table = of_match_ptr(omap_rng_of_match),
|
||
},
|
||
.probe = omap_rng_probe,
|
||
.remove = omap_rng_remove,
|
||
};
|
||
|
||
module_platform_driver(omap_rng_driver);
|
||
MODULE_ALIAS("platform:omap_rng");
|
||
MODULE_AUTHOR("Deepak Saxena (and others)");
|
||
MODULE_LICENSE("GPL");
|