![Ben Hutchings](/assets/img/avatar_default.png)
Insertion of the Falcon hash is unreliable. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
657 lines
19 KiB
C
657 lines
19 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2009 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include "net_driver.h"
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#include "bitfield.h"
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#include "efx.h"
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#include "nic.h"
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#include "mac.h"
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#include "spi.h"
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#include "regs.h"
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#include "io.h"
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#include "phy.h"
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#include "workarounds.h"
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#include "mcdi.h"
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#include "mcdi_pcol.h"
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/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
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static void siena_init_wol(struct efx_nic *efx);
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static void siena_push_irq_moderation(struct efx_channel *channel)
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{
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efx_dword_t timer_cmd;
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if (channel->irq_moderation)
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EFX_POPULATE_DWORD_2(timer_cmd,
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FRF_CZ_TC_TIMER_MODE,
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FFE_CZ_TIMER_MODE_INT_HLDOFF,
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FRF_CZ_TC_TIMER_VAL,
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channel->irq_moderation - 1);
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else
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EFX_POPULATE_DWORD_2(timer_cmd,
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FRF_CZ_TC_TIMER_MODE,
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FFE_CZ_TIMER_MODE_DIS,
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FRF_CZ_TC_TIMER_VAL, 0);
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efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
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channel->channel);
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}
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static void siena_push_multicast_hash(struct efx_nic *efx)
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{
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WARN_ON(!mutex_is_locked(&efx->mac_lock));
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efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
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efx->multicast_hash.byte, sizeof(efx->multicast_hash),
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NULL, 0, NULL);
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}
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static int siena_mdio_write(struct net_device *net_dev,
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int prtad, int devad, u16 addr, u16 value)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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uint32_t status;
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int rc;
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rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
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addr, value, &status);
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if (rc)
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return rc;
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if (status != MC_CMD_MDIO_STATUS_GOOD)
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return -EIO;
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return 0;
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}
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static int siena_mdio_read(struct net_device *net_dev,
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int prtad, int devad, u16 addr)
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{
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struct efx_nic *efx = netdev_priv(net_dev);
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uint16_t value;
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uint32_t status;
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int rc;
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rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
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addr, &value, &status);
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if (rc)
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return rc;
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if (status != MC_CMD_MDIO_STATUS_GOOD)
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return -EIO;
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return (int)value;
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}
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/* This call is responsible for hooking in the MAC and PHY operations */
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static int siena_probe_port(struct efx_nic *efx)
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{
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int rc;
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/* Hook in PHY operations table */
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efx->phy_op = &efx_mcdi_phy_ops;
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/* Set up MDIO structure for PHY */
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efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
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efx->mdio.mdio_read = siena_mdio_read;
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efx->mdio.mdio_write = siena_mdio_write;
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/* Fill out MDIO structure, loopback modes, and initial link state */
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rc = efx->phy_op->probe(efx);
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if (rc != 0)
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return rc;
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/* Allocate buffer for stats */
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rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
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MC_CMD_MAC_NSTATS * sizeof(u64));
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if (rc)
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return rc;
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netif_dbg(efx, probe, efx->net_dev,
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"stats buffer at %llx (virt %p phys %llx)\n",
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(u64)efx->stats_buffer.dma_addr,
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efx->stats_buffer.addr,
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(u64)virt_to_phys(efx->stats_buffer.addr));
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efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
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return 0;
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}
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void siena_remove_port(struct efx_nic *efx)
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{
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efx->phy_op->remove(efx);
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efx_nic_free_buffer(efx, &efx->stats_buffer);
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}
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static const struct efx_nic_register_test siena_register_tests[] = {
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{ FR_AZ_ADR_REGION,
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EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
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{ FR_CZ_USR_EV_CFG,
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EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_CFG,
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EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
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{ FR_AZ_TX_CFG,
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EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
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{ FR_AZ_TX_RESERVED,
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EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
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{ FR_AZ_SRM_TX_DC_CFG,
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EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_DC_CFG,
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EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_DC_PF_WM,
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EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_BZ_DP_CTRL,
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EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_BZ_RX_RSS_TKEY,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG1,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG2,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG3,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
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};
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static int siena_test_registers(struct efx_nic *efx)
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{
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return efx_nic_test_registers(efx, siena_register_tests,
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ARRAY_SIZE(siena_register_tests));
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}
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/**************************************************************************
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*
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* Device reset
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*
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**************************************************************************
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*/
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static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
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{
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int rc;
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/* Recover from a failed assertion pre-reset */
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rc = efx_mcdi_handle_assertion(efx);
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if (rc)
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return rc;
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if (method == RESET_TYPE_WORLD)
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return efx_mcdi_reset_mc(efx);
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else
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return efx_mcdi_reset_port(efx);
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}
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static int siena_probe_nvconfig(struct efx_nic *efx)
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{
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int rc;
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rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
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if (rc)
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return rc;
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return 0;
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}
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static int siena_probe_nic(struct efx_nic *efx)
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{
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struct siena_nic_data *nic_data;
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bool already_attached = 0;
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efx_oword_t reg;
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int rc;
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/* Allocate storage for hardware specific data */
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nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
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if (!nic_data)
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return -ENOMEM;
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efx->nic_data = nic_data;
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if (efx_nic_fpga_ver(efx) != 0) {
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netif_err(efx, probe, efx->net_dev,
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"Siena FPGA not supported\n");
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rc = -ENODEV;
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goto fail1;
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}
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efx_reado(efx, ®, FR_AZ_CS_DEBUG);
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efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
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efx_mcdi_init(efx);
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/* Recover from a failed assertion before probing */
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rc = efx_mcdi_handle_assertion(efx);
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if (rc)
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goto fail1;
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rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Failed to read MCPU firmware version - rc %d\n", rc);
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goto fail1; /* MCPU absent? */
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}
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/* Let the BMC know that the driver is now in charge of link and
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* filter settings. We must do this before we reset the NIC */
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rc = efx_mcdi_drv_attach(efx, true, &already_attached);
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if (rc) {
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netif_err(efx, probe, efx->net_dev,
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"Unable to register driver with MCPU\n");
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goto fail2;
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}
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if (already_attached)
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/* Not a fatal error */
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netif_err(efx, probe, efx->net_dev,
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"Host already registered with MCPU\n");
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/* Now we can reset the NIC */
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rc = siena_reset_hw(efx, RESET_TYPE_ALL);
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if (rc) {
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netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
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goto fail3;
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}
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siena_init_wol(efx);
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/* Allocate memory for INT_KER */
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rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
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if (rc)
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goto fail4;
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BUG_ON(efx->irq_status.dma_addr & 0x0f);
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netif_dbg(efx, probe, efx->net_dev,
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"INT_KER at %llx (virt %p phys %llx)\n",
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(unsigned long long)efx->irq_status.dma_addr,
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efx->irq_status.addr,
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(unsigned long long)virt_to_phys(efx->irq_status.addr));
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/* Read in the non-volatile configuration */
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rc = siena_probe_nvconfig(efx);
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if (rc == -EINVAL) {
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netif_err(efx, probe, efx->net_dev,
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"NVRAM is invalid therefore using defaults\n");
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efx->phy_type = PHY_TYPE_NONE;
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efx->mdio.prtad = MDIO_PRTAD_NONE;
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} else if (rc) {
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goto fail5;
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}
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return 0;
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fail5:
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efx_nic_free_buffer(efx, &efx->irq_status);
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fail4:
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fail3:
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efx_mcdi_drv_attach(efx, false, NULL);
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fail2:
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fail1:
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kfree(efx->nic_data);
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return rc;
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}
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/* This call performs hardware-specific global initialisation, such as
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* defining the descriptor cache sizes and number of RSS channels.
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* It does not set up any buffers, descriptor rings or event queues.
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*/
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static int siena_init_nic(struct efx_nic *efx)
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{
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efx_oword_t temp;
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int rc;
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/* Recover from a failed assertion post-reset */
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rc = efx_mcdi_handle_assertion(efx);
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if (rc)
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return rc;
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/* Squash TX of packets of 16 bytes or less */
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efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
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/* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
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* descriptors (which is bad).
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*/
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efx_reado(efx, &temp, FR_AZ_TX_CFG);
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EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
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EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_CFG);
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efx_reado(efx, &temp, FR_AZ_RX_CFG);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
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/* Enable hash insertion. This is broken for the 'Falcon' hash
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* if IPv6 hashing is also enabled, so also select Toeplitz
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* TCP/IPv4 and IPv4 hashes. */
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
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efx_writeo(efx, &temp, FR_AZ_RX_CFG);
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/* Set hash key for IPv4 */
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memcpy(&temp, efx->rx_hash_key, sizeof(temp));
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efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
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/* Enable IPv6 RSS */
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BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
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2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
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FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
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memcpy(&temp, efx->rx_hash_key, sizeof(temp));
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efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
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memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
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efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
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EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
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FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
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memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
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FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
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efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
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if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
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/* No MCDI operation has been defined to set thresholds */
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netif_err(efx, hw, efx->net_dev,
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"ignoring RX flow control thresholds\n");
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/* Enable event logging */
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rc = efx_mcdi_log_ctrl(efx, true, false, 0);
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if (rc)
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return rc;
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/* Set destination of both TX and RX Flush events */
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EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
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efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
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EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
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efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
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efx_nic_init_common(efx);
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return 0;
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}
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static void siena_remove_nic(struct efx_nic *efx)
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{
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efx_nic_free_buffer(efx, &efx->irq_status);
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siena_reset_hw(efx, RESET_TYPE_ALL);
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/* Relinquish the device back to the BMC */
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if (efx_nic_has_mc(efx))
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efx_mcdi_drv_attach(efx, false, NULL);
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/* Tear down the private nic state */
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kfree(efx->nic_data);
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efx->nic_data = NULL;
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}
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#define STATS_GENERATION_INVALID ((u64)(-1))
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static int siena_try_update_nic_stats(struct efx_nic *efx)
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{
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u64 *dma_stats;
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struct efx_mac_stats *mac_stats;
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u64 generation_start;
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u64 generation_end;
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mac_stats = &efx->mac_stats;
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dma_stats = (u64 *)efx->stats_buffer.addr;
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generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
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if (generation_end == STATS_GENERATION_INVALID)
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return 0;
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rmb();
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#define MAC_STAT(M, D) \
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mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
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MAC_STAT(tx_bytes, TX_BYTES);
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MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
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mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
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mac_stats->tx_bad_bytes);
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MAC_STAT(tx_packets, TX_PKTS);
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MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
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MAC_STAT(tx_pause, TX_PAUSE_PKTS);
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MAC_STAT(tx_control, TX_CONTROL_PKTS);
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MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
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MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
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MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
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MAC_STAT(tx_lt64, TX_LT64_PKTS);
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MAC_STAT(tx_64, TX_64_PKTS);
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MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
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MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
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MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
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MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
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MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
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MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
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MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
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mac_stats->tx_collision = 0;
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MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
|
|
MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
|
|
MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
|
|
MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
|
|
MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
|
|
mac_stats->tx_collision = (mac_stats->tx_single_collision +
|
|
mac_stats->tx_multiple_collision +
|
|
mac_stats->tx_excessive_collision +
|
|
mac_stats->tx_late_collision);
|
|
MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
|
|
MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
|
|
MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
|
|
MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
|
|
MAC_STAT(rx_bytes, RX_BYTES);
|
|
MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
|
|
mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
|
|
mac_stats->rx_bad_bytes);
|
|
MAC_STAT(rx_packets, RX_PKTS);
|
|
MAC_STAT(rx_good, RX_GOOD_PKTS);
|
|
mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
|
|
MAC_STAT(rx_pause, RX_PAUSE_PKTS);
|
|
MAC_STAT(rx_control, RX_CONTROL_PKTS);
|
|
MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
|
|
MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
|
|
MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
|
|
MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
|
|
MAC_STAT(rx_64, RX_64_PKTS);
|
|
MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
|
|
MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
|
|
MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
|
|
MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
|
|
MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
|
|
MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
|
|
MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
|
|
mac_stats->rx_bad_lt64 = 0;
|
|
mac_stats->rx_bad_64_to_15xx = 0;
|
|
mac_stats->rx_bad_15xx_to_jumbo = 0;
|
|
MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
|
|
MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
|
|
mac_stats->rx_missed = 0;
|
|
MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
|
|
MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
|
|
MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
|
|
MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
|
|
MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
|
|
mac_stats->rx_good_lt64 = 0;
|
|
|
|
efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
|
|
|
|
#undef MAC_STAT
|
|
|
|
rmb();
|
|
generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
|
|
if (generation_end != generation_start)
|
|
return -EAGAIN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void siena_update_nic_stats(struct efx_nic *efx)
|
|
{
|
|
int retry;
|
|
|
|
/* If we're unlucky enough to read statistics wduring the DMA, wait
|
|
* up to 10ms for it to finish (typically takes <500us) */
|
|
for (retry = 0; retry < 100; ++retry) {
|
|
if (siena_try_update_nic_stats(efx) == 0)
|
|
return;
|
|
udelay(100);
|
|
}
|
|
|
|
/* Use the old values instead */
|
|
}
|
|
|
|
static void siena_start_nic_stats(struct efx_nic *efx)
|
|
{
|
|
u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
|
|
|
|
dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
|
|
|
|
efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
|
|
MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
|
|
}
|
|
|
|
static void siena_stop_nic_stats(struct efx_nic *efx)
|
|
{
|
|
efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
|
|
}
|
|
|
|
void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
|
|
{
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
snprintf(buf, len, "%u.%u.%u.%u",
|
|
(unsigned int)(nic_data->fw_version >> 48),
|
|
(unsigned int)(nic_data->fw_version >> 32 & 0xffff),
|
|
(unsigned int)(nic_data->fw_version >> 16 & 0xffff),
|
|
(unsigned int)(nic_data->fw_version & 0xffff));
|
|
}
|
|
|
|
/**************************************************************************
|
|
*
|
|
* Wake on LAN
|
|
*
|
|
**************************************************************************
|
|
*/
|
|
|
|
static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
|
|
{
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
|
|
wol->supported = WAKE_MAGIC;
|
|
if (nic_data->wol_filter_id != -1)
|
|
wol->wolopts = WAKE_MAGIC;
|
|
else
|
|
wol->wolopts = 0;
|
|
memset(&wol->sopass, 0, sizeof(wol->sopass));
|
|
}
|
|
|
|
|
|
static int siena_set_wol(struct efx_nic *efx, u32 type)
|
|
{
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
int rc;
|
|
|
|
if (type & ~WAKE_MAGIC)
|
|
return -EINVAL;
|
|
|
|
if (type & WAKE_MAGIC) {
|
|
if (nic_data->wol_filter_id != -1)
|
|
efx_mcdi_wol_filter_remove(efx,
|
|
nic_data->wol_filter_id);
|
|
rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
|
|
&nic_data->wol_filter_id);
|
|
if (rc)
|
|
goto fail;
|
|
|
|
pci_wake_from_d3(efx->pci_dev, true);
|
|
} else {
|
|
rc = efx_mcdi_wol_filter_reset(efx);
|
|
nic_data->wol_filter_id = -1;
|
|
pci_wake_from_d3(efx->pci_dev, false);
|
|
if (rc)
|
|
goto fail;
|
|
}
|
|
|
|
return 0;
|
|
fail:
|
|
netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
|
|
__func__, type, rc);
|
|
return rc;
|
|
}
|
|
|
|
|
|
static void siena_init_wol(struct efx_nic *efx)
|
|
{
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
int rc;
|
|
|
|
rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
|
|
|
|
if (rc != 0) {
|
|
/* If it failed, attempt to get into a synchronised
|
|
* state with MC by resetting any set WoL filters */
|
|
efx_mcdi_wol_filter_reset(efx);
|
|
nic_data->wol_filter_id = -1;
|
|
} else if (nic_data->wol_filter_id != -1) {
|
|
pci_wake_from_d3(efx->pci_dev, true);
|
|
}
|
|
}
|
|
|
|
|
|
/**************************************************************************
|
|
*
|
|
* Revision-dependent attributes used by efx.c and nic.c
|
|
*
|
|
**************************************************************************
|
|
*/
|
|
|
|
struct efx_nic_type siena_a0_nic_type = {
|
|
.probe = siena_probe_nic,
|
|
.remove = siena_remove_nic,
|
|
.init = siena_init_nic,
|
|
.fini = efx_port_dummy_op_void,
|
|
.monitor = NULL,
|
|
.reset = siena_reset_hw,
|
|
.probe_port = siena_probe_port,
|
|
.remove_port = siena_remove_port,
|
|
.prepare_flush = efx_port_dummy_op_void,
|
|
.update_stats = siena_update_nic_stats,
|
|
.start_stats = siena_start_nic_stats,
|
|
.stop_stats = siena_stop_nic_stats,
|
|
.set_id_led = efx_mcdi_set_id_led,
|
|
.push_irq_moderation = siena_push_irq_moderation,
|
|
.push_multicast_hash = siena_push_multicast_hash,
|
|
.reconfigure_port = efx_mcdi_phy_reconfigure,
|
|
.get_wol = siena_get_wol,
|
|
.set_wol = siena_set_wol,
|
|
.resume_wol = siena_init_wol,
|
|
.test_registers = siena_test_registers,
|
|
.test_nvram = efx_mcdi_nvram_test_all,
|
|
.default_mac_ops = &efx_mcdi_mac_operations,
|
|
|
|
.revision = EFX_REV_SIENA_A0,
|
|
.mem_map_size = (FR_CZ_MC_TREG_SMEM +
|
|
FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
|
|
.txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
|
|
.rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
|
|
.buf_tbl_base = FR_BZ_BUF_FULL_TBL,
|
|
.evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
|
|
.evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
|
|
.max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
|
|
.rx_buffer_hash_size = 0x10,
|
|
.rx_buffer_padding = 0,
|
|
.max_interrupt_mode = EFX_INT_MODE_MSIX,
|
|
.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
|
|
* interrupt handler only supports 32
|
|
* channels */
|
|
.tx_dc_base = 0x88000,
|
|
.rx_dc_base = 0x68000,
|
|
.offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
|
|
NETIF_F_RXHASH),
|
|
.reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
|
|
};
|