3db11feffc
Convert the driver from the outdated omap_pm_set_max_mpu_wakeup_lat API to the new PM QoS API. Since the constraint is on the MPU subsystem, use the PM_QOS_CPU_DMA_LATENCY class of PM QoS. The resulting MPU constraints are used by cpuidle to decide the next power state of the MPU subsystem. The I2C device latency timing is derived from the FIFO size and the clock speed and so is applicable to all OMAP SoCs. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Shubhrajyoti D <shubhrajyoti@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
#ifndef __I2C_OMAP_H__
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#define __I2C_OMAP_H__
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#include <linux/platform_device.h>
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/*
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* Version 2 of the I2C peripheral unit has a different register
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* layout and extra registers. The ID register in the V2 peripheral
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* unit on the OMAP4430 reports the same ID as the V1 peripheral
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* unit on the OMAP3530, so we must inform the driver which IP
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* version we know it is running on from platform / cpu-specific
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* code using these constants in the hwmod class definition.
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*/
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#define OMAP_I2C_IP_VERSION_1 1
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#define OMAP_I2C_IP_VERSION_2 2
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/* struct omap_i2c_bus_platform_data .flags meanings */
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#define OMAP_I2C_FLAG_NO_FIFO BIT(0)
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#define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1)
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#define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2)
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#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3)
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#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4)
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#define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5)
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#define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6)
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/* how the CPU address bus must be translated for I2C unit access */
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#define OMAP_I2C_FLAG_BUS_SHIFT_NONE 0
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#define OMAP_I2C_FLAG_BUS_SHIFT_1 BIT(7)
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#define OMAP_I2C_FLAG_BUS_SHIFT_2 BIT(8)
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#define OMAP_I2C_FLAG_BUS_SHIFT__SHIFT 7
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struct omap_i2c_bus_platform_data {
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u32 clkrate;
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u32 rev;
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u32 flags;
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};
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#endif
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