![Bart Van Assche](/assets/img/avatar_default.png)
Some but not all architectures provide set_dma_ops(). Move dma_ops from struct dev_archdata into struct device such that it becomes possible on all architectures to configure dma_ops per device. Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Juergen Gross <jgross@suse.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Russell King <linux@armlinux.org.uk> Cc: x86@kernel.org Signed-off-by: Doug Ledford <dledford@redhat.com>
388 lines
9.6 KiB
C
388 lines
9.6 KiB
C
/*
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* Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
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*
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* Provide default implementations of the DMA mapping callbacks for
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* directly mapped busses.
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*/
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-debug.h>
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#include <linux/gfp.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <asm/vio.h>
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#include <asm/bug.h>
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#include <asm/machdep.h>
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#include <asm/swiotlb.h>
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#include <asm/iommu.h>
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/*
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* Generic direct DMA implementation
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*
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* This implementation supports a per-device offset that can be applied if
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* the address at which memory is visible to devices is not 0. Platform code
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* can set archdata.dma_data to an unsigned long holding the offset. By
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* default the offset is PCI_DRAM_OFFSET.
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*/
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static u64 __maybe_unused get_pfn_limit(struct device *dev)
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{
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u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
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struct dev_archdata __maybe_unused *sd = &dev->archdata;
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#ifdef CONFIG_SWIOTLB
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if (sd->max_direct_dma_addr && dev->dma_ops == &swiotlb_dma_ops)
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pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
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#endif
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return pfn;
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}
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static int dma_direct_dma_supported(struct device *dev, u64 mask)
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{
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#ifdef CONFIG_PPC64
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u64 limit = get_dma_offset(dev) + (memblock_end_of_DRAM() - 1);
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/* Limit fits in the mask, we are good */
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if (mask >= limit)
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return 1;
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#ifdef CONFIG_FSL_SOC
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/* Freescale gets another chance via ZONE_DMA/ZONE_DMA32, however
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* that will have to be refined if/when they support iommus
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*/
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return 1;
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#endif
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/* Sorry ... */
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return 0;
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#else
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return 1;
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#endif
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}
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void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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void *ret;
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#ifdef CONFIG_NOT_COHERENT_CACHE
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ret = __dma_alloc_coherent(dev, size, dma_handle, flag);
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if (ret == NULL)
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return NULL;
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*dma_handle += get_dma_offset(dev);
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return ret;
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#else
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struct page *page;
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int node = dev_to_node(dev);
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#ifdef CONFIG_FSL_SOC
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u64 pfn = get_pfn_limit(dev);
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int zone;
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/*
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* This code should be OK on other platforms, but we have drivers that
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* don't set coherent_dma_mask. As a workaround we just ifdef it. This
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* whole routine needs some serious cleanup.
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*/
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zone = dma_pfn_limit_to_zone(pfn);
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if (zone < 0) {
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dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
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__func__, pfn);
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return NULL;
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}
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switch (zone) {
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case ZONE_DMA:
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flag |= GFP_DMA;
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break;
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#ifdef CONFIG_ZONE_DMA32
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case ZONE_DMA32:
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flag |= GFP_DMA32;
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break;
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#endif
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};
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#endif /* CONFIG_FSL_SOC */
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/* ignore region specifiers */
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flag &= ~(__GFP_HIGHMEM);
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page = alloc_pages_node(node, flag, get_order(size));
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if (page == NULL)
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return NULL;
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ret = page_address(page);
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memset(ret, 0, size);
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*dma_handle = __pa(ret) + get_dma_offset(dev);
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return ret;
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#endif
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}
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void __dma_direct_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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#ifdef CONFIG_NOT_COHERENT_CACHE
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__dma_free_coherent(size, vaddr);
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#else
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free_pages((unsigned long)vaddr, get_order(size));
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#endif
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}
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static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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struct iommu_table *iommu;
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/* The coherent mask may be smaller than the real mask, check if
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* we can really use the direct ops
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*/
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if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_direct_alloc_coherent(dev, size, dma_handle,
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flag, attrs);
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/* Ok we can't ... do we have an iommu ? If not, fail */
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iommu = get_iommu_table_base(dev);
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if (!iommu)
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return NULL;
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/* Try to use the iommu */
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return iommu_alloc_coherent(dev, iommu, size, dma_handle,
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dev->coherent_dma_mask, flag,
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dev_to_node(dev));
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}
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static void dma_direct_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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struct iommu_table *iommu;
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/* See comments in dma_direct_alloc_coherent() */
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if (dma_direct_dma_supported(dev, dev->coherent_dma_mask))
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return __dma_direct_free_coherent(dev, size, vaddr, dma_handle,
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attrs);
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/* Maybe we used an iommu ... */
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iommu = get_iommu_table_base(dev);
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/* If we hit that we should have never allocated in the first
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* place so how come we are freeing ?
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*/
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if (WARN_ON(!iommu))
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return;
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iommu_free_coherent(iommu, size, vaddr, dma_handle);
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}
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int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t handle, size_t size,
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unsigned long attrs)
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{
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unsigned long pfn;
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#ifdef CONFIG_NOT_COHERENT_CACHE
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
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#else
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pfn = page_to_pfn(virt_to_page(cpu_addr));
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#endif
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return remap_pfn_range(vma, vma->vm_start,
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pfn + vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i) {
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sg->dma_address = sg_phys(sg) + get_dma_offset(dev);
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sg->dma_length = sg->length;
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if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
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continue;
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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return nents;
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}
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static void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction,
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unsigned long attrs)
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{
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}
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static u64 dma_direct_get_required_mask(struct device *dev)
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{
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u64 end, mask;
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end = memblock_end_of_DRAM() + get_dma_offset(dev);
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mask = 1ULL << (fls64(end) - 1);
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mask += mask - 1;
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return mask;
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}
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static inline dma_addr_t dma_direct_map_page(struct device *dev,
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struct page *page,
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unsigned long offset,
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size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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BUG_ON(dir == DMA_NONE);
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if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
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__dma_sync_page(page, offset, size, dir);
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return page_to_phys(page) + offset + get_dma_offset(dev);
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}
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static inline void dma_direct_unmap_page(struct device *dev,
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dma_addr_t dma_address,
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size_t size,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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}
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#ifdef CONFIG_NOT_COHERENT_CACHE
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static inline void dma_direct_sync_sg(struct device *dev,
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struct scatterlist *sgl, int nents,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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for_each_sg(sgl, sg, nents, i)
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__dma_sync_page(sg_page(sg), sg->offset, sg->length, direction);
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}
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static inline void dma_direct_sync_single(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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#endif
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const struct dma_map_ops dma_direct_ops = {
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.alloc = dma_direct_alloc_coherent,
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.free = dma_direct_free_coherent,
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.mmap = dma_direct_mmap_coherent,
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.map_sg = dma_direct_map_sg,
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.unmap_sg = dma_direct_unmap_sg,
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.dma_supported = dma_direct_dma_supported,
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.map_page = dma_direct_map_page,
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.unmap_page = dma_direct_unmap_page,
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.get_required_mask = dma_direct_get_required_mask,
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#ifdef CONFIG_NOT_COHERENT_CACHE
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.sync_single_for_cpu = dma_direct_sync_single,
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.sync_single_for_device = dma_direct_sync_single,
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.sync_sg_for_cpu = dma_direct_sync_sg,
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.sync_sg_for_device = dma_direct_sync_sg,
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#endif
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};
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EXPORT_SYMBOL(dma_direct_ops);
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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if (!dma_supported(dev, mask)) {
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/*
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* We need to special case the direct DMA ops which can
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* support a fallback for coherent allocations. There
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* is no dma_op->set_coherent_mask() so we have to do
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* things the hard way:
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*/
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if (get_dma_ops(dev) != &dma_direct_ops ||
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get_iommu_table_base(dev) == NULL ||
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!dma_iommu_dma_supported(dev, mask))
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return -EIO;
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}
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dev->coherent_dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_coherent_mask);
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#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
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int __dma_set_mask(struct device *dev, u64 dma_mask)
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{
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const struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
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return dma_ops->set_dma_mask(dev, dma_mask);
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if (!dev->dma_mask || !dma_supported(dev, dma_mask))
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return -EIO;
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*dev->dma_mask = dma_mask;
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return 0;
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}
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int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (ppc_md.dma_set_mask)
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return ppc_md.dma_set_mask(dev, dma_mask);
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if (dev_is_pci(dev)) {
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struct pci_dev *pdev = to_pci_dev(dev);
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struct pci_controller *phb = pci_bus_to_host(pdev->bus);
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if (phb->controller_ops.dma_set_mask)
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return phb->controller_ops.dma_set_mask(pdev, dma_mask);
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}
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return __dma_set_mask(dev, dma_mask);
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}
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EXPORT_SYMBOL(dma_set_mask);
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u64 __dma_get_required_mask(struct device *dev)
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{
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const struct dma_map_ops *dma_ops = get_dma_ops(dev);
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if (unlikely(dma_ops == NULL))
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return 0;
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if (dma_ops->get_required_mask)
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return dma_ops->get_required_mask(dev);
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return DMA_BIT_MASK(8 * sizeof(dma_addr_t));
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}
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u64 dma_get_required_mask(struct device *dev)
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{
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if (ppc_md.dma_get_required_mask)
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return ppc_md.dma_get_required_mask(dev);
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if (dev_is_pci(dev)) {
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struct pci_dev *pdev = to_pci_dev(dev);
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struct pci_controller *phb = pci_bus_to_host(pdev->bus);
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if (phb->controller_ops.dma_get_required_mask)
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return phb->controller_ops.dma_get_required_mask(pdev);
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}
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return __dma_get_required_mask(dev);
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}
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EXPORT_SYMBOL_GPL(dma_get_required_mask);
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static int __init dma_init(void)
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{
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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#ifdef CONFIG_PCI
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dma_debug_add_bus(&pci_bus_type);
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#endif
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#ifdef CONFIG_IBMVIO
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dma_debug_add_bus(&vio_bus_type);
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#endif
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return 0;
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}
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fs_initcall(dma_init);
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