128f2d567f
In preparation for adding more operation types to the ioat3 path the driver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api will hand xor->memcpy->xor chains to the driver with the 'fence' flag set on the first xor and the memcpy operation. This flag in turn sets the 'fence' flag in the descriptor control field telling the hardware that future descriptors in the chain depend on the result of the current descriptor, so wait for all writes to complete before starting the next operation. Note that ioat1 does not prefetch the descriptor chain, so does not require/support fenced operations. Signed-off-by: Dan Williams <dan.j.williams@intel.com> |
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| .. | ||
| ioat | ||
| ipu | ||
| dmaengine.c | ||
| dmatest.c | ||
| dw_dmac.c | ||
| dw_dmac_regs.h | ||
| fsldma.c | ||
| fsldma.h | ||
| iop-adma.c | ||
| iovlock.c | ||
| Kconfig | ||
| Makefile | ||
| mv_xor.c | ||
| mv_xor.h | ||