3bcb03f3a7
Move the initialisation of the CP0.Wired register implemented by Toshiba TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where it belongs, correcting code structure and making sure initialisation does not rely on `tx39_cache_init' being called before `tlb_init' to work correctly. Make `r3k_have_wired_reg' static as it's no longer externally referred to; remove a stale declaration too. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10195/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
64 lines
1.5 KiB
C
64 lines
1.5 KiB
C
/*
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* Dump R3000 TLB for debugging purposes.
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*
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* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
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* Copyright (C) 1999 by Silicon Graphics, Inc.
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* Copyright (C) 1999 by Harald Koerfgen
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tlbdebug.h>
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static void dump_tlb(int first, int last)
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{
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int i;
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unsigned int asid;
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unsigned long entryhi, entrylo0;
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asid = read_c0_entryhi() & ASID_MASK;
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for (i = first; i <= last; i++) {
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write_c0_index(i<<8);
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__asm__ __volatile__(
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".set\tnoreorder\n\t"
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"tlbr\n\t"
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"nop\n\t"
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".set\treorder");
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entryhi = read_c0_entryhi();
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entrylo0 = read_c0_entrylo0();
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/* Unused entries have a virtual address of KSEG0. */
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if ((entryhi & PAGE_MASK) != KSEG0 &&
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(entrylo0 & R3K_ENTRYLO_G ||
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(entryhi & ASID_MASK) == asid)) {
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/*
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* Only print entries in use
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*/
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printk("Index: %2d ", i);
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printk("va=%08lx asid=%08lx"
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" [pa=%06lx n=%d d=%d v=%d g=%d]",
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entryhi & PAGE_MASK,
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entryhi & ASID_MASK,
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entrylo0 & PAGE_MASK,
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(entrylo0 & R3K_ENTRYLO_N) ? 1 : 0,
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(entrylo0 & R3K_ENTRYLO_D) ? 1 : 0,
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(entrylo0 & R3K_ENTRYLO_V) ? 1 : 0,
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(entrylo0 & R3K_ENTRYLO_G) ? 1 : 0);
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}
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}
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printk("\n");
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write_c0_entryhi(asid);
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}
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void dump_tlb_all(void)
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{
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dump_tlb(0, current_cpu_data.tlbsize - 1);
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}
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