![Hiroshi Doyu](/assets/img/avatar_default.png)
Use the Tegra30 CAR binding header (tegra30-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra30-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
601 lines
16 KiB
Plaintext
601 lines
16 KiB
Plaintext
#include <dt-bindings/clock/tegra30-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra30";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uarta;
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serial1 = &uartb;
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serial2 = &uartc;
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serial3 = &uartd;
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serial4 = &uarte;
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};
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host1x {
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compatible = "nvidia,tegra30-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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mpe {
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compatible = "nvidia,tegra30-mpe";
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reg = <0x54040000 0x00040000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_MPE>;
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};
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vi {
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compatible = "nvidia,tegra30-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_VI>;
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};
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epp {
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compatible = "nvidia,tegra30-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_EPP>;
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};
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isp {
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compatible = "nvidia,tegra30-isp";
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reg = <0x54100000 0x00040000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_ISP>;
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};
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gr2d {
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compatible = "nvidia,tegra30-gr2d";
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reg = <0x54140000 0x00040000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_GR2D>;
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};
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gr3d {
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compatible = "nvidia,tegra30-gr3d";
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reg = <0x54180000 0x00040000>;
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clocks = <&tegra_car 24 &tegra_car 98>;
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clock-names = "3d", "3d2";
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};
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dc@54200000 {
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compatible = "nvidia,tegra30-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_DISP1>,
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<&tegra_car TEGRA30_CLK_PLL_P>;
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clock-names = "disp1", "parent";
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra30-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_DISP2>,
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<&tegra_car TEGRA30_CLK_PLL_P>;
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clock-names = "disp2", "parent";
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rgb {
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status = "disabled";
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};
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};
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hdmi {
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compatible = "nvidia,tegra30-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_HDMI>,
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<&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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status = "disabled";
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};
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tvo {
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compatible = "nvidia,tegra30-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_TVO>;
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status = "disabled";
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};
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dsi {
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compatible = "nvidia,tegra30-dsi";
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reg = <0x54300000 0x00040000>;
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clocks = <&tegra_car TEGRA30_CLK_DSIA>;
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status = "disabled";
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};
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};
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timer@50004600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x50040600 0x20>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&tegra_car TEGRA30_CLK_TWD>;
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};
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intc: interrupt-controller {
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compatible = "arm,cortex-a9-gic";
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reg = <0x50041000 0x1000
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0x50040100 0x0100>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0x50043000 0x1000>;
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arm,data-latency = <6 6 2>;
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arm,tag-latency = <5 5 2>;
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cache-unified;
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cache-level = <2>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_TIMER>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra30-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
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};
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ahb: ahb {
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compatible = "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
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};
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gpio: gpio {
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compatible = "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra30-pinmux";
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reg = <0x70000868 0xd4 /* Pad control registers */
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0x70003000 0x3e4>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
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*/
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uarta: serial@70006000 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 8>;
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clocks = <&tegra_car TEGRA30_CLK_UARTA>;
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 9>;
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clocks = <&tegra_car TEGRA30_CLK_UARTB>;
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 10>;
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clocks = <&tegra_car TEGRA30_CLK_UARTC>;
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 19>;
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clocks = <&tegra_car TEGRA30_CLK_UARTD>;
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status = "disabled";
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};
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uarte: serial@70006400 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 20>;
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clocks = <&tegra_car TEGRA30_CLK_UARTE>;
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status = "disabled";
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};
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pwm: pwm {
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compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA30_CLK_PWM>;
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status = "disabled";
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};
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rtc {
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compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA30_CLK_RTC>;
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_I2C1>,
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<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_I2C2>,
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<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_I2C3>,
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<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_I2C4>,
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<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_I2C5>,
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<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
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clock-names = "div-clk", "fast-clk";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000d400 0x200>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC1>;
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status = "disabled";
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};
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spi@7000d600 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000d600 0x200>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC2>;
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status = "disabled";
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};
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spi@7000d800 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000d800 0x200>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 17>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC3>;
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status = "disabled";
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};
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spi@7000da00 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000da00 0x200>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 18>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC4>;
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status = "disabled";
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};
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spi@7000dc00 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000dc00 0x200>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 27>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC5>;
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status = "disabled";
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};
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spi@7000de00 {
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compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
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reg = <0x7000de00 0x200>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,dma-request-selector = <&apbdma 28>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA30_CLK_SBC6>;
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status = "disabled";
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};
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kbc {
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compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
|
|
reg = <0x7000e200 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_KBC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmc {
|
|
compatible = "nvidia,tegra30-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
};
|
|
|
|
memory-controller {
|
|
compatible = "nvidia,tegra30-mc";
|
|
reg = <0x7000f000 0x010
|
|
0x7000f03c 0x1b4
|
|
0x7000f200 0x028
|
|
0x7000f284 0x17c>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iommu {
|
|
compatible = "nvidia,tegra30-smmu";
|
|
reg = <0x7000f010 0x02c
|
|
0x7000f1f0 0x010
|
|
0x7000f228 0x05c>;
|
|
nvidia,#asids = <4>; /* # of ASIDs */
|
|
dma-window = <0 0x40000000>; /* IOVA start & length */
|
|
nvidia,ahb = <&ahb>;
|
|
};
|
|
|
|
ahub {
|
|
compatible = "nvidia,tegra30-ahub";
|
|
reg = <0x70080000 0x200
|
|
0x70080200 0x100>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 1>;
|
|
clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
|
|
<&tegra_car TEGRA30_CLK_APBIF>,
|
|
<&tegra_car TEGRA30_CLK_I2S0>,
|
|
<&tegra_car TEGRA30_CLK_I2S1>,
|
|
<&tegra_car TEGRA30_CLK_I2S2>,
|
|
<&tegra_car TEGRA30_CLK_I2S3>,
|
|
<&tegra_car TEGRA30_CLK_I2S4>,
|
|
<&tegra_car TEGRA30_CLK_DAM0>,
|
|
<&tegra_car TEGRA30_CLK_DAM1>,
|
|
<&tegra_car TEGRA30_CLK_DAM2>,
|
|
<&tegra_car TEGRA30_CLK_SPDIF_IN>;
|
|
clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
|
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
|
"spdif_in";
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
tegra_i2s0: i2s@70080300 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080300 0x100>;
|
|
nvidia,ahub-cif-ids = <4 4>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70080400 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080400 0x100>;
|
|
nvidia,ahub-cif-ids = <5 5>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70080500 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080500 0x100>;
|
|
nvidia,ahub-cif-ids = <6 6>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s3: i2s@70080600 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080600 0x100>;
|
|
nvidia,ahub-cif-ids = <7 7>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s4: i2s@70080700 {
|
|
compatible = "nvidia,tegra30-i2s";
|
|
reg = <0x70080700 0x100>;
|
|
nvidia,ahub-cif-ids = <8 8>;
|
|
clocks = <&tegra_car TEGRA30_CLK_I2S4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sdhci@78000000 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000000 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000200 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000200 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000400 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000400 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@78000600 {
|
|
compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
|
|
reg = <0x78000600 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|