![Phil Edworthy](/assets/img/avatar_default.png)
The Synopsys I2C Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Gareth Williams <gareth.williams.jx@renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
377 lines
9.1 KiB
C
377 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Synopsys DesignWare I2C adapter driver.
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/swab.h>
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#include "i2c-designware-core.h"
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static char *abort_sources[] = {
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[ABRT_7B_ADDR_NOACK] =
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"slave address not acknowledged (7bit mode)",
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[ABRT_10ADDR1_NOACK] =
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"first address byte not acknowledged (10bit mode)",
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[ABRT_10ADDR2_NOACK] =
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"second address byte not acknowledged (10bit mode)",
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[ABRT_TXDATA_NOACK] =
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"data not acknowledged",
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[ABRT_GCALL_NOACK] =
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"no acknowledgement for a general call",
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[ABRT_GCALL_READ] =
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"read after general call",
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[ABRT_SBYTE_ACKDET] =
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"start byte acknowledged",
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[ABRT_SBYTE_NORSTRT] =
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"trying to send start byte when restart is disabled",
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[ABRT_10B_RD_NORSTRT] =
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"trying to read when restart is disabled (10bit mode)",
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[ABRT_MASTER_DIS] =
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"trying to use disabled adapter",
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[ARB_LOST] =
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"lost arbitration",
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[ABRT_SLAVE_FLUSH_TXFIFO] =
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"read command so flush old data in the TX FIFO",
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[ABRT_SLAVE_ARBLOST] =
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"slave lost the bus while transmitting data to a remote master",
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[ABRT_SLAVE_RD_INTX] =
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"incorrect slave-transmitter mode configuration",
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};
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u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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{
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u32 value;
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if (dev->flags & ACCESS_16BIT)
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value = readw_relaxed(dev->base + offset) |
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(readw_relaxed(dev->base + offset + 2) << 16);
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else
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value = readl_relaxed(dev->base + offset);
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if (dev->flags & ACCESS_SWAP)
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return swab32(value);
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else
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return value;
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}
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void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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{
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if (dev->flags & ACCESS_SWAP)
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b = swab32(b);
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if (dev->flags & ACCESS_16BIT) {
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writew_relaxed((u16)b, dev->base + offset);
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writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
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} else {
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writel_relaxed(b, dev->base + offset);
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}
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}
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/**
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* i2c_dw_set_reg_access() - Set register access flags
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* @dev: device private data
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*
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* Autodetects needed register access mode and sets access flags accordingly.
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* This must be called before doing any other register access.
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*/
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int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
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{
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u32 reg;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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reg = dw_readl(dev, DW_IC_COMP_TYPE);
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i2c_dw_release_lock(dev);
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if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
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/* Configure register endianess access */
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dev->flags |= ACCESS_SWAP;
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} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
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/* Configure register access mode 16bit */
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dev->flags |= ACCESS_16BIT;
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} else if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev,
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"Unknown Synopsys component type: 0x%08x\n", reg);
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return -ENODEV;
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}
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return 0;
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}
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u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_dw_scl_lcnt().
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*/
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return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
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- 3 + offset;
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}
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u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
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}
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int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
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{
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u32 reg;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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/* Configure SDA Hold Time if required */
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reg = dw_readl(dev, DW_IC_COMP_VERSION);
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if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
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if (!dev->sda_hold_time) {
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/* Keep previous hold time setting if no one set it */
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dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
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}
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/*
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* Workaround for avoiding TX arbitration lost in case I2C
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* slave pulls SDA down "too quickly" after falling egde of
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* SCL by enabling non-zero SDA RX hold. Specification says it
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* extends incoming SDA low to high transition while SCL is
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* high but it apprears to help also above issue.
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*/
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if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
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dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
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dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
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dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
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dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
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} else if (dev->set_sda_hold_time) {
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dev->set_sda_hold_time(dev);
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} else if (dev->sda_hold_time) {
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dev_warn(dev->dev,
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"Hardware too old to adjust SDA hold time.\n");
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dev->sda_hold_time = 0;
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}
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i2c_dw_release_lock(dev);
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return 0;
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}
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void __i2c_dw_disable(struct dw_i2c_dev *dev)
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{
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int timeout = 100;
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do {
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__i2c_dw_disable_nowait(dev);
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/*
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* The enable status register may be unimplemented, but
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* in that case this test reads zero and exits the loop.
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*/
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if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == 0)
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return;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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usleep_range(25, 250);
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} while (timeout--);
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dev_warn(dev->dev, "timeout in disabling adapter\n");
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}
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unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
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{
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/*
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* Clock is not necessary if we got LCNT/HCNT values directly from
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* the platform code.
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*/
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if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
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return 0;
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return dev->get_clk_rate_khz(dev);
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}
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int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
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{
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int ret;
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if (IS_ERR(dev->clk))
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return PTR_ERR(dev->clk);
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if (prepare) {
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/* Optional interface clock */
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ret = clk_prepare_enable(dev->pclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(dev->clk);
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if (ret)
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clk_disable_unprepare(dev->pclk);
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return ret;
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}
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clk_disable_unprepare(dev->clk);
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clk_disable_unprepare(dev->pclk);
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return 0;
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}
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EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
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int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
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{
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int ret;
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if (!dev->acquire_lock)
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return 0;
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ret = dev->acquire_lock();
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if (!ret)
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return 0;
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dev_err(dev->dev, "couldn't acquire bus ownership\n");
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return ret;
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}
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void i2c_dw_release_lock(struct dw_i2c_dev *dev)
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{
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if (dev->release_lock)
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dev->release_lock();
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}
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/*
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* Waiting for bus not busy
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*/
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int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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{
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int timeout = TIMEOUT;
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while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
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if (timeout <= 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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i2c_recover_bus(&dev->adapter);
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if (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY)
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return -ETIMEDOUT;
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return 0;
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}
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timeout--;
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usleep_range(1000, 1100);
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}
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return 0;
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}
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int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
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{
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unsigned long abort_source = dev->abort_source;
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int i;
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if (abort_source & DW_IC_TX_ABRT_NOACK) {
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for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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dev_dbg(dev->dev,
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"%s: %s\n", __func__, abort_sources[i]);
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return -EREMOTEIO;
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}
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for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
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dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
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if (abort_source & DW_IC_TX_ARB_LOST)
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return -EAGAIN;
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else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
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return -EINVAL; /* wrong msgs[] data */
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else
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return -EIO;
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}
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u32 i2c_dw_func(struct i2c_adapter *adap)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
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return dev->functionality;
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}
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void i2c_dw_disable(struct dw_i2c_dev *dev)
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{
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/* Disable controller */
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__i2c_dw_disable(dev);
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/* Disable all interupts */
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dw_writel(dev, 0, DW_IC_INTR_MASK);
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dw_readl(dev, DW_IC_CLR_INTR);
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}
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void i2c_dw_disable_int(struct dw_i2c_dev *dev)
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{
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dw_writel(dev, 0, DW_IC_INTR_MASK);
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}
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u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
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{
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return dw_readl(dev, DW_IC_COMP_PARAM_1);
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}
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EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
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MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
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MODULE_LICENSE("GPL");
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