![Jingoo Han](/assets/img/avatar_default.png)
Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
520 lines
12 KiB
C
520 lines
12 KiB
C
/*
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* drivers/mtd/nand/au1550nd.c
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*
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* Copyright (C) 2004 Embedded Edge, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1550nd.h>
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struct au1550nd_ctx {
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struct mtd_info info;
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struct nand_chip chip;
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int cs;
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void __iomem *base;
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void (*write_byte)(struct mtd_info *, u_char);
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};
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/**
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* au_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*
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* read function for 8bit buswidth
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*/
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static u_char au_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = readb(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_byte - write one byte to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 8it buswidth
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*/
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static void au_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writeb(byte, this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_byte16 - read one byte endianness aware from the chip
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* @mtd: MTD device structure
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*
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* read function for 16bit buswidth with endianness conversion
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*/
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static u_char au_read_byte16(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
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au_sync();
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return ret;
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}
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/**
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* au_write_byte16 - write one byte endianness aware to the chip
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* @mtd: MTD device structure
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* @byte: pointer to data byte to write
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*
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* write function for 16bit buswidth with endianness conversion
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*/
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static void au_write_byte16(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
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au_sync();
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}
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/**
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* au_read_word - read one word from the chip
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* @mtd: MTD device structure
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*
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* read function for 16bit buswidth without endianness conversion
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*/
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static u16 au_read_word(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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u16 ret = readw(this->IO_ADDR_R);
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au_sync();
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return ret;
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}
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/**
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* au_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 8bit buswidth
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*/
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static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++) {
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writeb(buf[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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* au_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 8bit buswidth
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*/
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static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i = 0; i < len; i++) {
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buf[i] = readb(this->IO_ADDR_R);
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au_sync();
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}
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}
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/**
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* au_write_buf16 - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*
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* write function for 16bit buswidth
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*/
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static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++) {
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writew(p[i], this->IO_ADDR_W);
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au_sync();
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}
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}
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/**
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* au_read_buf16 - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*
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* read function for 16bit buswidth
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*/
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static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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u16 *p = (u16 *) buf;
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len >>= 1;
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for (i = 0; i < len; i++) {
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p[i] = readw(this->IO_ADDR_R);
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au_sync();
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}
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}
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
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struct nand_chip *this = mtd->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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break;
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
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break;
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
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/* FIXME: Nobody knows why this is necessary,
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* but it works only that way */
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udelay(1);
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break;
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case NAND_CTL_SETNCE:
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/* assert (force assert) chip enable */
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au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
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break;
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case NAND_CTL_CLRNCE:
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/* deassert chip enable */
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au_writel(0, MEM_STNDCTL);
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break;
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}
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this->IO_ADDR_R = this->IO_ADDR_W;
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/* Drain the writebuffer */
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au_sync();
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}
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int au1550_device_ready(struct mtd_info *mtd)
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{
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int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
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au_sync();
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return ret;
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}
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/**
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* au1550_select_chip - control -CE line
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* Forbid driving -CE manually permitting the NAND controller to do this.
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* Keeping -CE asserted during the whole sector reads interferes with the
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* NOR flash and PCMCIA drivers as it causes contention on the static bus.
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* We only have to hold -CE low for the NAND read commands since the flash
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* chip needs it to be asserted during chip not ready time but the NAND
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* controller keeps it released.
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*
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* @mtd: MTD device structure
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* @chip: chipnumber to select, -1 for deselect
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*/
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static void au1550_select_chip(struct mtd_info *mtd, int chip)
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{
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}
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/**
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* au1550_command - Send command to NAND device
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* @mtd: MTD device structure
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* @command: the command to be sent
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* @column: the column address for this command, -1 if none
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* @page_addr: the page address for this command, -1 if none
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*/
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static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
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{
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struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
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struct nand_chip *this = mtd->priv;
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int ce_override = 0, i;
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unsigned long flags = 0;
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/* Begin command latch cycle */
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au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->writesize) {
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/* OOB area */
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column -= mtd->writesize;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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ctx->write_byte(mtd, readcmd);
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}
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ctx->write_byte(mtd, command);
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/* Set ALE and clear CLE to start address cycle */
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au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
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if (column != -1 || page_addr != -1) {
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au1550_hwcontrol(mtd, NAND_CTL_SETALE);
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (this->options & NAND_BUSWIDTH_16)
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column >>= 1;
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ctx->write_byte(mtd, column);
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}
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if (page_addr != -1) {
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ctx->write_byte(mtd, (u8)(page_addr & 0xff));
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if (command == NAND_CMD_READ0 ||
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command == NAND_CMD_READ1 ||
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command == NAND_CMD_READOOB) {
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/*
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* NAND controller will release -CE after
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* the last address byte is written, so we'll
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* have to forcibly assert it. No interrupts
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* are allowed while we do this as we don't
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* want the NOR flash or PCMCIA drivers to
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* steal our precious bytes of data...
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*/
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ce_override = 1;
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local_irq_save(flags);
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au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
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}
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ctx->write_byte(mtd, (u8)(page_addr >> 8));
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/* One more address cycle for devices > 32MiB */
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if (this->chipsize > (32 << 20))
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ctx->write_byte(mtd,
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((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
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}
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/*
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* Program and erase have their own busy handlers.
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* Status and sequential in need no delay.
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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break;
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case NAND_CMD_READ0:
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case NAND_CMD_READ1:
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case NAND_CMD_READOOB:
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/* Check if we're really driving -CE low (just in case) */
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if (unlikely(!ce_override))
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break;
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/* Apply a short delay always to ensure that we do wait tWB. */
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ndelay(100);
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/* Wait for a chip to become ready... */
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for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
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udelay(1);
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/* Release -CE and re-enable interrupts. */
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au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
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local_irq_restore(flags);
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return;
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}
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/* Apply this short delay always to ensure that we do wait tWB. */
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ndelay(100);
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while(!this->dev_ready(mtd));
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}
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static int find_nand_cs(unsigned long nand_base)
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{
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void __iomem *base =
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(void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
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unsigned long addr, staddr, start, mask, end;
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int i;
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for (i = 0; i < 4; i++) {
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addr = 0x1000 + (i * 0x10); /* CSx */
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staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
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/* figure out the decoded range of this CS */
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start = (staddr << 4) & 0xfffc0000;
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mask = (staddr << 18) & 0xfffc0000;
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end = (start | (start - 1)) & ~(start ^ mask);
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if ((nand_base >= start) && (nand_base < end))
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return i;
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}
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return -ENODEV;
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}
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static int au1550nd_probe(struct platform_device *pdev)
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{
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struct au1550nd_platdata *pd;
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struct au1550nd_ctx *ctx;
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struct nand_chip *this;
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struct resource *r;
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int ret, cs;
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pd = dev_get_platdata(&pdev->dev);
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if (!pd) {
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dev_err(&pdev->dev, "missing platform data\n");
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return -ENODEV;
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}
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx) {
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dev_err(&pdev->dev, "no memory for NAND context\n");
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return -ENOMEM;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no NAND memory resource\n");
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ret = -ENODEV;
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goto out1;
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}
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if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
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dev_err(&pdev->dev, "cannot claim NAND memory area\n");
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ret = -ENOMEM;
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goto out1;
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}
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ctx->base = ioremap_nocache(r->start, 0x1000);
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if (!ctx->base) {
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dev_err(&pdev->dev, "cannot remap NAND memory area\n");
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ret = -ENODEV;
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goto out2;
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}
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this = &ctx->chip;
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ctx->info.priv = this;
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ctx->info.owner = THIS_MODULE;
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/* figure out which CS# r->start belongs to */
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cs = find_nand_cs(r->start);
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if (cs < 0) {
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dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
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ret = -ENODEV;
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goto out3;
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}
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ctx->cs = cs;
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this->dev_ready = au1550_device_ready;
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this->select_chip = au1550_select_chip;
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this->cmdfunc = au1550_command;
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/* 30 us command delay time */
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this->chip_delay = 30;
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this->ecc.mode = NAND_ECC_SOFT;
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if (pd->devwidth)
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this->options |= NAND_BUSWIDTH_16;
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this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
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ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
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this->read_word = au_read_word;
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this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
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this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
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ret = nand_scan(&ctx->info, 1);
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if (ret) {
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dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
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goto out3;
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}
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mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
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return 0;
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out3:
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iounmap(ctx->base);
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out2:
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release_mem_region(r->start, resource_size(r));
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out1:
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kfree(ctx);
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return ret;
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}
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static int au1550nd_remove(struct platform_device *pdev)
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{
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struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
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struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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nand_release(&ctx->info);
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iounmap(ctx->base);
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release_mem_region(r->start, 0x1000);
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kfree(ctx);
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return 0;
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}
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static struct platform_driver au1550nd_driver = {
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.driver = {
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.name = "au1550-nand",
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.owner = THIS_MODULE,
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},
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.probe = au1550nd_probe,
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.remove = au1550nd_remove,
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};
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module_platform_driver(au1550nd_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Embedded Edge, LLC");
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MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
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