![Jingoo Han](/assets/img/avatar_default.png)
Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
320 lines
7.7 KiB
C
320 lines
7.7 KiB
C
/*
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* drivers/mtd/nand/gpio.c
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*
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* Updated, and converted to generic GPIO based driver by Russell King.
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*
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* Written by Ben Dooks <ben@simtec.co.uk>
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* Based on 2.4 version by Mark Whittaker
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*
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* © 2004 Simtec Electronics
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*
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* Device driver for NAND connected via GPIO
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand-gpio.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_gpio.h>
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struct gpiomtd {
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void __iomem *io_sync;
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struct mtd_info mtd_info;
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struct nand_chip nand_chip;
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struct gpio_nand_platdata plat;
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};
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#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
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#ifdef CONFIG_ARM
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/* gpio_nand_dosync()
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*
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* Make sure the GPIO state changes occur in-order with writes to NAND
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* memory region.
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* Needed on PXA due to bus-reordering within the SoC itself (see section on
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* I/O ordering in PXA manual (section 2.3, p35)
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*/
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static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
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{
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unsigned long tmp;
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if (gpiomtd->io_sync) {
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/*
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* Linux memory barriers don't cater for what's required here.
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* What's required is what's here - a read from a separate
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* region with a dependency on that read.
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*/
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tmp = readl(gpiomtd->io_sync);
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asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
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}
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}
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#else
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static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
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#endif
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static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
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gpio_nand_dosync(gpiomtd);
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if (ctrl & NAND_CTRL_CHANGE) {
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gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
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gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
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gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
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gpio_nand_dosync(gpiomtd);
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}
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if (cmd == NAND_CMD_NONE)
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return;
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writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
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gpio_nand_dosync(gpiomtd);
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}
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static int gpio_nand_devready(struct mtd_info *mtd)
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{
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
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return gpio_get_value(gpiomtd->plat.gpio_rdy);
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}
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#ifdef CONFIG_OF
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static const struct of_device_id gpio_nand_id_table[] = {
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{ .compatible = "gpio-control-nand" },
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{}
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};
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MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
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static int gpio_nand_get_config_of(const struct device *dev,
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struct gpio_nand_platdata *plat)
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{
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u32 val;
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if (!dev->of_node)
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return -ENODEV;
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if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
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if (val == 2) {
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plat->options |= NAND_BUSWIDTH_16;
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} else if (val != 1) {
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dev_err(dev, "invalid bank-width %u\n", val);
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return -EINVAL;
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}
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}
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plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
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plat->gpio_nce = of_get_gpio(dev->of_node, 1);
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plat->gpio_ale = of_get_gpio(dev->of_node, 2);
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plat->gpio_cle = of_get_gpio(dev->of_node, 3);
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plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
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if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
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plat->chip_delay = val;
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return 0;
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}
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static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
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{
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struct resource *r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
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u64 addr;
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if (!r || of_property_read_u64(pdev->dev.of_node,
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"gpio-control-nand,io-sync-reg", &addr))
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return NULL;
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r->start = addr;
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r->end = r->start + 0x3;
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r->flags = IORESOURCE_MEM;
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return r;
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}
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#else /* CONFIG_OF */
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static inline int gpio_nand_get_config_of(const struct device *dev,
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struct gpio_nand_platdata *plat)
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{
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return -ENOSYS;
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}
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static inline struct resource *
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gpio_nand_get_io_sync_of(struct platform_device *pdev)
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{
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return NULL;
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}
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#endif /* CONFIG_OF */
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static inline int gpio_nand_get_config(const struct device *dev,
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struct gpio_nand_platdata *plat)
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{
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int ret = gpio_nand_get_config_of(dev, plat);
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if (!ret)
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return ret;
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if (dev_get_platdata(dev)) {
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memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
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return 0;
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}
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return -EINVAL;
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}
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static inline struct resource *
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gpio_nand_get_io_sync(struct platform_device *pdev)
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{
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struct resource *r = gpio_nand_get_io_sync_of(pdev);
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if (r)
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return r;
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return platform_get_resource(pdev, IORESOURCE_MEM, 1);
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}
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static int gpio_nand_remove(struct platform_device *pdev)
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{
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struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
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nand_release(&gpiomtd->mtd_info);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
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gpio_set_value(gpiomtd->plat.gpio_nce, 1);
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return 0;
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}
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static int gpio_nand_probe(struct platform_device *pdev)
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{
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struct gpiomtd *gpiomtd;
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struct nand_chip *chip;
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struct resource *res;
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struct mtd_part_parser_data ppdata = {};
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int ret = 0;
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if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
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return -EINVAL;
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gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
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if (!gpiomtd) {
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dev_err(&pdev->dev, "failed to create NAND MTD\n");
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return -ENOMEM;
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}
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chip = &gpiomtd->nand_chip;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(chip->IO_ADDR_R))
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return PTR_ERR(chip->IO_ADDR_R);
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res = gpio_nand_get_io_sync(pdev);
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if (res) {
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gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gpiomtd->io_sync))
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return PTR_ERR(gpiomtd->io_sync);
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}
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ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
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if (ret)
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return ret;
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ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
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if (ret)
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return ret;
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gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
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ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
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"NAND NWP");
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if (ret)
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return ret;
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}
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ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
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if (ret)
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return ret;
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gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
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ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
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if (ret)
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return ret;
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gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
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if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
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ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
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"NAND RDY");
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if (ret)
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return ret;
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gpio_direction_input(gpiomtd->plat.gpio_rdy);
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chip->dev_ready = gpio_nand_devready;
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}
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chip->IO_ADDR_W = chip->IO_ADDR_R;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->options = gpiomtd->plat.options;
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chip->chip_delay = gpiomtd->plat.chip_delay;
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chip->cmd_ctrl = gpio_nand_cmd_ctrl;
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gpiomtd->mtd_info.priv = chip;
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gpiomtd->mtd_info.owner = THIS_MODULE;
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platform_set_drvdata(pdev, gpiomtd);
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
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if (nand_scan(&gpiomtd->mtd_info, 1)) {
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ret = -ENXIO;
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goto err_wp;
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}
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if (gpiomtd->plat.adjust_parts)
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gpiomtd->plat.adjust_parts(&gpiomtd->plat,
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gpiomtd->mtd_info.size);
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ppdata.of_node = pdev->dev.of_node;
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ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
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gpiomtd->plat.parts,
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gpiomtd->plat.num_parts);
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if (!ret)
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return 0;
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err_wp:
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if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
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gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
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return ret;
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}
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static struct platform_driver gpio_nand_driver = {
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.probe = gpio_nand_probe,
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.remove = gpio_nand_remove,
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.driver = {
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.name = "gpio-nand",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(gpio_nand_id_table),
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},
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};
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module_platform_driver(gpio_nand_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
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MODULE_DESCRIPTION("GPIO NAND Driver");
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