![Linus Torvalds](/assets/img/avatar_default.png)
Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJdKVoLAAoJEFHr6jzI4aWA0kIP/A6shIbbE7H5W2hFrqt/PPPK 3+VrvPKbOFF+W6hcE/RgSZmEnUo0svdNjHUd/eMfFS1vb/uRt2QDdrsHUNNwURQL M2mcLXFwYpnjSjb/XMgDbHpAQxjeGfTdYLonUIejN7Rk8KQUeLyKQ3SBn6kfMc46 DnUUcPcjuRGaETUmVuZZ4e40ZWbJp8PKDrSJOuUrTPXMaK5ciNbZk5mCWXGbYl6G BMQAyv4ld/417rNTjBEP/T2foMJtioAt4W6mtlgdkOTdIEZnFU67nNxDBthNSu2c 95+I+/sML4KOp1R4yhqLSLIDDbc3bg3c99hLGij0d948z3bkSZ8bwnPaUuy70C4v U8rvl/+N6C6H3DgSsPE/Gnkd8DnudqWY8nULc+8p3fXljGwww6/Qgt+6yCUn8BdW WgixkSjKgjDmzTw8trIUNEqORrTVle7cM2hIyIK2Q5T4kWzNQxrLZ/x/3wgoYjUa 1KwIzaRo5JKZ9D3pJnJ5U+knE2/90rJIyfcp0W6ygyJsWKi2GNmq1eN3sKOw0IxH Tg86RENIA/rEMErNOfP45sLteMuTR7of7peCG3yumIOZqsDVYAzerpvtSgip2cvK aG+9HcYlBFOOOF9Dabi8GXsTBLXLfwiyjjLSpA9eXPwW8KObgiNfTZa7ujjTPvis 4mk9oukFTFUpfhsMmI3T =3dBZ -----END PGP SIGNATURE----- Merge tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "Notable changes: - Removal of the NPU DMA code, used by the out-of-tree Nvidia driver, as well as some other functions only used by drivers that haven't (yet?) made it upstream. - A fix for a bug in our handling of hardware watchpoints (eg. perf record -e mem: ...) which could lead to register corruption and kernel crashes. - Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for vmalloc when using the Radix MMU. - A large but incremental rewrite of our exception handling code to use gas macros rather than multiple levels of nested CPP macros. And the usual small fixes, cleanups and improvements. Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab, Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann, Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz, Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N. Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj Jitindar Singh, Thiago Jung Bauermann, YueHaibing" * tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (163 commits) powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state. powerpc/eeh: Handle hugepages in ioremap space ocxl: Update for AFU descriptor template version 1.1 powerpc/boot: pass CONFIG options in a simpler and more robust way powerpc/boot: add {get, put}_unaligned_be32 to xz_config.h powerpc/irq: Don't WARN continuously in arch_local_irq_restore() powerpc/module64: Use symbolic instructions names. powerpc/module32: Use symbolic instructions names. powerpc: Move PPC_HA() PPC_HI() and PPC_LO() to ppc-opcode.h powerpc/module64: Fix comment in R_PPC64_ENTRY handling powerpc/boot: Add lzo support for uImage powerpc/boot: Add lzma support for uImage powerpc/boot: don't force gzipped uImage powerpc/8xx: Add microcode patch to move SMC parameter RAM. powerpc/8xx: Use IO accessors in microcode programming. powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c powerpc/8xx: refactor programming of microcode CPM params. powerpc/8xx: refactor printing of microcode patch name. powerpc/8xx: Refactor microcode write powerpc/8xx: refactor writing of CPM microcode arrays ...
865 lines
22 KiB
C
865 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/cpu.h>
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#include <linux/kvm_host.h>
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#include <linux/preempt.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/memblock.h>
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#include <linux/sizes.h>
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#include <linux/cma.h>
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#include <linux/bitops.h>
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#include <asm/asm-prototypes.h>
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#include <asm/cputable.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/archrandom.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/dbell.h>
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#include <asm/cputhreads.h>
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#include <asm/io.h>
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#include <asm/opal.h>
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#include <asm/smp.h>
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#define KVM_CMA_CHUNK_ORDER 18
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#include "book3s_xics.h"
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#include "book3s_xive.h"
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/*
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* The XIVE module will populate these when it loads
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*/
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unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu);
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unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server);
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int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server,
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unsigned long mfrr);
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int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr);
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int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr);
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EXPORT_SYMBOL_GPL(__xive_vm_h_xirr);
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EXPORT_SYMBOL_GPL(__xive_vm_h_ipoll);
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EXPORT_SYMBOL_GPL(__xive_vm_h_ipi);
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EXPORT_SYMBOL_GPL(__xive_vm_h_cppr);
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EXPORT_SYMBOL_GPL(__xive_vm_h_eoi);
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/*
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* Hash page table alignment on newer cpus(CPU_FTR_ARCH_206)
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* should be power of 2.
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*/
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#define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */
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/*
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* By default we reserve 5% of memory for hash pagetable allocation.
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*/
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static unsigned long kvm_cma_resv_ratio = 5;
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static struct cma *kvm_cma;
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static int __init early_parse_kvm_cma_resv(char *p)
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{
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pr_debug("%s(%s)\n", __func__, p);
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if (!p)
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return -EINVAL;
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return kstrtoul(p, 0, &kvm_cma_resv_ratio);
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}
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early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv);
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struct page *kvm_alloc_hpt_cma(unsigned long nr_pages)
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{
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VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
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return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES),
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false);
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}
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EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma);
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void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages)
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{
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cma_release(kvm_cma, page, nr_pages);
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}
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EXPORT_SYMBOL_GPL(kvm_free_hpt_cma);
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/**
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* kvm_cma_reserve() - reserve area for kvm hash pagetable
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*
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* This function reserves memory from early allocator. It should be
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* called by arch specific code once the memblock allocator
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* has been activated and all other subsystems have already allocated/reserved
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* memory.
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*/
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void __init kvm_cma_reserve(void)
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{
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unsigned long align_size;
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struct memblock_region *reg;
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phys_addr_t selected_size = 0;
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/*
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* We need CMA reservation only when we are in HV mode
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*/
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return;
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/*
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* We cannot use memblock_phys_mem_size() here, because
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* memblock_analyze() has not been called yet.
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*/
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for_each_memblock(memory, reg)
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selected_size += memblock_region_memory_end_pfn(reg) -
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memblock_region_memory_base_pfn(reg);
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selected_size = (selected_size * kvm_cma_resv_ratio / 100) << PAGE_SHIFT;
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if (selected_size) {
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pr_debug("%s: reserving %ld MiB for global area\n", __func__,
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(unsigned long)selected_size / SZ_1M);
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align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
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cma_declare_contiguous(0, selected_size, 0, align_size,
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KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma",
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&kvm_cma);
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}
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}
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/*
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* Real-mode H_CONFER implementation.
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* We check if we are the only vcpu out of this virtual core
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* still running in the guest and not ceded. If so, we pop up
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* to the virtual-mode implementation; if not, just return to
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* the guest.
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*/
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long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target,
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unsigned int yield_count)
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{
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struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
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int ptid = local_paca->kvm_hstate.ptid;
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int threads_running;
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int threads_ceded;
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int threads_conferring;
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u64 stop = get_tb() + 10 * tb_ticks_per_usec;
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int rv = H_SUCCESS; /* => don't yield */
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set_bit(ptid, &vc->conferring_threads);
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while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) {
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threads_running = VCORE_ENTRY_MAP(vc);
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threads_ceded = vc->napping_threads;
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threads_conferring = vc->conferring_threads;
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if ((threads_ceded | threads_conferring) == threads_running) {
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rv = H_TOO_HARD; /* => do yield */
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break;
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}
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}
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clear_bit(ptid, &vc->conferring_threads);
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return rv;
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}
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/*
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* When running HV mode KVM we need to block certain operations while KVM VMs
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* exist in the system. We use a counter of VMs to track this.
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*
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* One of the operations we need to block is onlining of secondaries, so we
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* protect hv_vm_count with get/put_online_cpus().
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*/
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static atomic_t hv_vm_count;
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void kvm_hv_vm_activated(void)
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{
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get_online_cpus();
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atomic_inc(&hv_vm_count);
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put_online_cpus();
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}
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EXPORT_SYMBOL_GPL(kvm_hv_vm_activated);
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void kvm_hv_vm_deactivated(void)
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{
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get_online_cpus();
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atomic_dec(&hv_vm_count);
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put_online_cpus();
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}
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EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated);
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bool kvm_hv_mode_active(void)
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{
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return atomic_read(&hv_vm_count) != 0;
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}
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extern int hcall_real_table[], hcall_real_table_end[];
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int kvmppc_hcall_impl_hv_realmode(unsigned long cmd)
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{
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cmd /= 4;
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if (cmd < hcall_real_table_end - hcall_real_table &&
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hcall_real_table[cmd])
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return 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode);
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int kvmppc_hwrng_present(void)
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{
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return powernv_hwrng_present();
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}
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EXPORT_SYMBOL_GPL(kvmppc_hwrng_present);
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long kvmppc_h_random(struct kvm_vcpu *vcpu)
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{
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int r;
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/* Only need to do the expensive mfmsr() on radix */
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if (kvm_is_radix(vcpu->kvm) && (mfmsr() & MSR_IR))
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r = powernv_get_random_long(&vcpu->arch.regs.gpr[4]);
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else
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r = powernv_get_random_real_mode(&vcpu->arch.regs.gpr[4]);
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if (r)
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return H_SUCCESS;
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return H_HARDWARE;
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}
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/*
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* Send an interrupt or message to another CPU.
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* The caller needs to include any barrier needed to order writes
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* to memory vs. the IPI/message.
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*/
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void kvmhv_rm_send_ipi(int cpu)
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{
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void __iomem *xics_phys;
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unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
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/* For a nested hypervisor, use the XICS via hcall */
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if (kvmhv_on_pseries()) {
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unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
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plpar_hcall_raw(H_IPI, retbuf, get_hard_smp_processor_id(cpu),
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IPI_PRIORITY);
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return;
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}
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/* On POWER9 we can use msgsnd for any destination cpu. */
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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msg |= get_hard_smp_processor_id(cpu);
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__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
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return;
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}
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/* On POWER8 for IPIs to threads in the same core, use msgsnd. */
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if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
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cpu_first_thread_sibling(cpu) ==
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cpu_first_thread_sibling(raw_smp_processor_id())) {
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msg |= cpu_thread_in_core(cpu);
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__asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
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return;
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}
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/* We should never reach this */
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if (WARN_ON_ONCE(xics_on_xive()))
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return;
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/* Else poke the target with an IPI */
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xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys;
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if (xics_phys)
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__raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
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else
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opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
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}
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/*
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* The following functions are called from the assembly code
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* in book3s_hv_rmhandlers.S.
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*/
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static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active)
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{
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int cpu = vc->pcpu;
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/* Order setting of exit map vs. msgsnd/IPI */
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smp_mb();
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for (; active; active >>= 1, ++cpu)
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if (active & 1)
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kvmhv_rm_send_ipi(cpu);
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}
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void kvmhv_commence_exit(int trap)
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{
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struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
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int ptid = local_paca->kvm_hstate.ptid;
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struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode;
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int me, ee, i, t;
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int cpu0;
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/* Set our bit in the threads-exiting-guest map in the 0xff00
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bits of vcore->entry_exit_map */
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me = 0x100 << ptid;
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do {
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ee = vc->entry_exit_map;
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} while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee);
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/* Are we the first here? */
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if ((ee >> 8) != 0)
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return;
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/*
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* Trigger the other threads in this vcore to exit the guest.
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* If this is a hypervisor decrementer interrupt then they
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* will be already on their way out of the guest.
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*/
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if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER)
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kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid));
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/*
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* If we are doing dynamic micro-threading, interrupt the other
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* subcores to pull them out of their guests too.
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*/
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if (!sip)
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return;
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for (i = 0; i < MAX_SUBCORES; ++i) {
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vc = sip->vc[i];
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if (!vc)
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break;
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do {
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ee = vc->entry_exit_map;
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/* Already asked to exit? */
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if ((ee >> 8) != 0)
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break;
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} while (cmpxchg(&vc->entry_exit_map, ee,
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ee | VCORE_EXIT_REQ) != ee);
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if ((ee >> 8) == 0)
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kvmhv_interrupt_vcore(vc, ee);
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}
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/*
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* On POWER9 when running a HPT guest on a radix host (sip != NULL),
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* we have to interrupt inactive CPU threads to get them to
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* restore the host LPCR value.
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*/
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if (sip->lpcr_req) {
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if (cmpxchg(&sip->do_restore, 0, 1) == 0) {
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vc = local_paca->kvm_hstate.kvm_vcore;
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cpu0 = vc->pcpu + ptid - local_paca->kvm_hstate.tid;
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for (t = 1; t < threads_per_core; ++t) {
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if (sip->napped[t])
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kvmhv_rm_send_ipi(cpu0 + t);
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}
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}
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}
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}
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struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv;
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EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv);
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#ifdef CONFIG_KVM_XICS
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static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap,
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u32 xisr)
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{
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int i;
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/*
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* We access the mapped array here without a lock. That
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* is safe because we never reduce the number of entries
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* in the array and we never change the v_hwirq field of
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* an entry once it is set.
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*
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* We have also carefully ordered the stores in the writer
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* and the loads here in the reader, so that if we find a matching
|
|
* hwirq here, the associated GSI and irq_desc fields are valid.
|
|
*/
|
|
for (i = 0; i < pimap->n_mapped; i++) {
|
|
if (xisr == pimap->mapped[i].r_hwirq) {
|
|
/*
|
|
* Order subsequent reads in the caller to serialize
|
|
* with the writer.
|
|
*/
|
|
smp_rmb();
|
|
return &pimap->mapped[i];
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* If we have an interrupt that's not an IPI, check if we have a
|
|
* passthrough adapter and if so, check if this external interrupt
|
|
* is for the adapter.
|
|
* We will attempt to deliver the IRQ directly to the target VCPU's
|
|
* ICP, the virtual ICP (based on affinity - the xive value in ICS).
|
|
*
|
|
* If the delivery fails or if this is not for a passthrough adapter,
|
|
* return to the host to handle this interrupt. We earlier
|
|
* saved a copy of the XIRR in the PACA, it will be picked up by
|
|
* the host ICP driver.
|
|
*/
|
|
static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
|
|
{
|
|
struct kvmppc_passthru_irqmap *pimap;
|
|
struct kvmppc_irq_map *irq_map;
|
|
struct kvm_vcpu *vcpu;
|
|
|
|
vcpu = local_paca->kvm_hstate.kvm_vcpu;
|
|
if (!vcpu)
|
|
return 1;
|
|
pimap = kvmppc_get_passthru_irqmap(vcpu->kvm);
|
|
if (!pimap)
|
|
return 1;
|
|
irq_map = get_irqmap(pimap, xisr);
|
|
if (!irq_map)
|
|
return 1;
|
|
|
|
/* We're handling this interrupt, generic code doesn't need to */
|
|
local_paca->kvm_hstate.saved_xirr = 0;
|
|
|
|
return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again);
|
|
}
|
|
|
|
#else
|
|
static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Determine what sort of external interrupt is pending (if any).
|
|
* Returns:
|
|
* 0 if no interrupt is pending
|
|
* 1 if an interrupt is pending that needs to be handled by the host
|
|
* 2 Passthrough that needs completion in the host
|
|
* -1 if there was a guest wakeup IPI (which has now been cleared)
|
|
* -2 if there is PCI passthrough external interrupt that was handled
|
|
*/
|
|
static long kvmppc_read_one_intr(bool *again);
|
|
|
|
long kvmppc_read_intr(void)
|
|
{
|
|
long ret = 0;
|
|
long rc;
|
|
bool again;
|
|
|
|
if (xive_enabled())
|
|
return 1;
|
|
|
|
do {
|
|
again = false;
|
|
rc = kvmppc_read_one_intr(&again);
|
|
if (rc && (ret == 0 || rc > ret))
|
|
ret = rc;
|
|
} while (again);
|
|
return ret;
|
|
}
|
|
|
|
static long kvmppc_read_one_intr(bool *again)
|
|
{
|
|
void __iomem *xics_phys;
|
|
u32 h_xirr;
|
|
__be32 xirr;
|
|
u32 xisr;
|
|
u8 host_ipi;
|
|
int64_t rc;
|
|
|
|
if (xive_enabled())
|
|
return 1;
|
|
|
|
/* see if a host IPI is pending */
|
|
host_ipi = local_paca->kvm_hstate.host_ipi;
|
|
if (host_ipi)
|
|
return 1;
|
|
|
|
/* Now read the interrupt from the ICP */
|
|
if (kvmhv_on_pseries()) {
|
|
unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
|
|
|
|
rc = plpar_hcall_raw(H_XIRR, retbuf, 0xFF);
|
|
xirr = cpu_to_be32(retbuf[0]);
|
|
} else {
|
|
xics_phys = local_paca->kvm_hstate.xics_phys;
|
|
rc = 0;
|
|
if (!xics_phys)
|
|
rc = opal_int_get_xirr(&xirr, false);
|
|
else
|
|
xirr = __raw_rm_readl(xics_phys + XICS_XIRR);
|
|
}
|
|
if (rc < 0)
|
|
return 1;
|
|
|
|
/*
|
|
* Save XIRR for later. Since we get control in reverse endian
|
|
* on LE systems, save it byte reversed and fetch it back in
|
|
* host endian. Note that xirr is the value read from the
|
|
* XIRR register, while h_xirr is the host endian version.
|
|
*/
|
|
h_xirr = be32_to_cpu(xirr);
|
|
local_paca->kvm_hstate.saved_xirr = h_xirr;
|
|
xisr = h_xirr & 0xffffff;
|
|
/*
|
|
* Ensure that the store/load complete to guarantee all side
|
|
* effects of loading from XIRR has completed
|
|
*/
|
|
smp_mb();
|
|
|
|
/* if nothing pending in the ICP */
|
|
if (!xisr)
|
|
return 0;
|
|
|
|
/* We found something in the ICP...
|
|
*
|
|
* If it is an IPI, clear the MFRR and EOI it.
|
|
*/
|
|
if (xisr == XICS_IPI) {
|
|
rc = 0;
|
|
if (kvmhv_on_pseries()) {
|
|
unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
|
|
|
|
plpar_hcall_raw(H_IPI, retbuf,
|
|
hard_smp_processor_id(), 0xff);
|
|
plpar_hcall_raw(H_EOI, retbuf, h_xirr);
|
|
} else if (xics_phys) {
|
|
__raw_rm_writeb(0xff, xics_phys + XICS_MFRR);
|
|
__raw_rm_writel(xirr, xics_phys + XICS_XIRR);
|
|
} else {
|
|
opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
|
|
rc = opal_int_eoi(h_xirr);
|
|
}
|
|
/* If rc > 0, there is another interrupt pending */
|
|
*again = rc > 0;
|
|
|
|
/*
|
|
* Need to ensure side effects of above stores
|
|
* complete before proceeding.
|
|
*/
|
|
smp_mb();
|
|
|
|
/*
|
|
* We need to re-check host IPI now in case it got set in the
|
|
* meantime. If it's clear, we bounce the interrupt to the
|
|
* guest
|
|
*/
|
|
host_ipi = local_paca->kvm_hstate.host_ipi;
|
|
if (unlikely(host_ipi != 0)) {
|
|
/* We raced with the host,
|
|
* we need to resend that IPI, bummer
|
|
*/
|
|
if (kvmhv_on_pseries()) {
|
|
unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
|
|
|
|
plpar_hcall_raw(H_IPI, retbuf,
|
|
hard_smp_processor_id(),
|
|
IPI_PRIORITY);
|
|
} else if (xics_phys)
|
|
__raw_rm_writeb(IPI_PRIORITY,
|
|
xics_phys + XICS_MFRR);
|
|
else
|
|
opal_int_set_mfrr(hard_smp_processor_id(),
|
|
IPI_PRIORITY);
|
|
/* Let side effects complete */
|
|
smp_mb();
|
|
return 1;
|
|
}
|
|
|
|
/* OK, it's an IPI for us */
|
|
local_paca->kvm_hstate.saved_xirr = 0;
|
|
return -1;
|
|
}
|
|
|
|
return kvmppc_check_passthru(xisr, xirr, again);
|
|
}
|
|
|
|
#ifdef CONFIG_KVM_XICS
|
|
static inline bool is_rm(void)
|
|
{
|
|
return !(mfmsr() & MSR_DR);
|
|
}
|
|
|
|
unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_xirr(vcpu);
|
|
if (unlikely(!__xive_vm_h_xirr))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_xirr(vcpu);
|
|
} else
|
|
return xics_rm_h_xirr(vcpu);
|
|
}
|
|
|
|
unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
vcpu->arch.regs.gpr[5] = get_tb();
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_xirr(vcpu);
|
|
if (unlikely(!__xive_vm_h_xirr))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_xirr(vcpu);
|
|
} else
|
|
return xics_rm_h_xirr(vcpu);
|
|
}
|
|
|
|
unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_ipoll(vcpu, server);
|
|
if (unlikely(!__xive_vm_h_ipoll))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_ipoll(vcpu, server);
|
|
} else
|
|
return H_TOO_HARD;
|
|
}
|
|
|
|
int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
|
unsigned long mfrr)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_ipi(vcpu, server, mfrr);
|
|
if (unlikely(!__xive_vm_h_ipi))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_ipi(vcpu, server, mfrr);
|
|
} else
|
|
return xics_rm_h_ipi(vcpu, server, mfrr);
|
|
}
|
|
|
|
int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_cppr(vcpu, cppr);
|
|
if (unlikely(!__xive_vm_h_cppr))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_cppr(vcpu, cppr);
|
|
} else
|
|
return xics_rm_h_cppr(vcpu, cppr);
|
|
}
|
|
|
|
int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
|
|
{
|
|
if (!kvmppc_xics_enabled(vcpu))
|
|
return H_TOO_HARD;
|
|
if (xics_on_xive()) {
|
|
if (is_rm())
|
|
return xive_rm_h_eoi(vcpu, xirr);
|
|
if (unlikely(!__xive_vm_h_eoi))
|
|
return H_NOT_AVAILABLE;
|
|
return __xive_vm_h_eoi(vcpu, xirr);
|
|
} else
|
|
return xics_rm_h_eoi(vcpu, xirr);
|
|
}
|
|
#endif /* CONFIG_KVM_XICS */
|
|
|
|
void kvmppc_bad_interrupt(struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* 100 could happen at any time, 200 can happen due to invalid real
|
|
* address access for example (or any time due to a hardware problem).
|
|
*/
|
|
if (TRAP(regs) == 0x100) {
|
|
get_paca()->in_nmi++;
|
|
system_reset_exception(regs);
|
|
get_paca()->in_nmi--;
|
|
} else if (TRAP(regs) == 0x200) {
|
|
machine_check_exception(regs);
|
|
} else {
|
|
die("Bad interrupt in KVM entry/exit code", regs, SIGABRT);
|
|
}
|
|
panic("Bad KVM trap");
|
|
}
|
|
|
|
/*
|
|
* Functions used to switch LPCR HR and UPRT bits on all threads
|
|
* when entering and exiting HPT guests on a radix host.
|
|
*/
|
|
|
|
#define PHASE_REALMODE 1 /* in real mode */
|
|
#define PHASE_SET_LPCR 2 /* have set LPCR */
|
|
#define PHASE_OUT_OF_GUEST 4 /* have finished executing in guest */
|
|
#define PHASE_RESET_LPCR 8 /* have reset LPCR to host value */
|
|
|
|
#define ALL(p) (((p) << 24) | ((p) << 16) | ((p) << 8) | (p))
|
|
|
|
static void wait_for_sync(struct kvm_split_mode *sip, int phase)
|
|
{
|
|
int thr = local_paca->kvm_hstate.tid;
|
|
|
|
sip->lpcr_sync.phase[thr] |= phase;
|
|
phase = ALL(phase);
|
|
while ((sip->lpcr_sync.allphases & phase) != phase) {
|
|
HMT_low();
|
|
barrier();
|
|
}
|
|
HMT_medium();
|
|
}
|
|
|
|
void kvmhv_p9_set_lpcr(struct kvm_split_mode *sip)
|
|
{
|
|
unsigned long rb, set;
|
|
|
|
/* wait for every other thread to get to real mode */
|
|
wait_for_sync(sip, PHASE_REALMODE);
|
|
|
|
/* Set LPCR and LPIDR */
|
|
mtspr(SPRN_LPCR, sip->lpcr_req);
|
|
mtspr(SPRN_LPID, sip->lpidr_req);
|
|
isync();
|
|
|
|
/* Invalidate the TLB on thread 0 */
|
|
if (local_paca->kvm_hstate.tid == 0) {
|
|
sip->do_set = 0;
|
|
asm volatile("ptesync" : : : "memory");
|
|
for (set = 0; set < POWER9_TLB_SETS_RADIX; ++set) {
|
|
rb = TLBIEL_INVAL_SET_LPID +
|
|
(set << TLBIEL_INVAL_SET_SHIFT);
|
|
asm volatile(PPC_TLBIEL(%0, %1, 0, 0, 0) : :
|
|
"r" (rb), "r" (0));
|
|
}
|
|
asm volatile("ptesync" : : : "memory");
|
|
}
|
|
|
|
/* indicate that we have done so and wait for others */
|
|
wait_for_sync(sip, PHASE_SET_LPCR);
|
|
/* order read of sip->lpcr_sync.allphases vs. sip->do_set */
|
|
smp_rmb();
|
|
}
|
|
|
|
/*
|
|
* Called when a thread that has been in the guest needs
|
|
* to reload the host LPCR value - but only on POWER9 when
|
|
* running a HPT guest on a radix host.
|
|
*/
|
|
void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip)
|
|
{
|
|
/* we're out of the guest... */
|
|
wait_for_sync(sip, PHASE_OUT_OF_GUEST);
|
|
|
|
mtspr(SPRN_LPID, 0);
|
|
mtspr(SPRN_LPCR, sip->host_lpcr);
|
|
isync();
|
|
|
|
if (local_paca->kvm_hstate.tid == 0) {
|
|
sip->do_restore = 0;
|
|
smp_wmb(); /* order store of do_restore vs. phase */
|
|
}
|
|
|
|
wait_for_sync(sip, PHASE_RESET_LPCR);
|
|
smp_mb();
|
|
local_paca->kvm_hstate.kvm_split_mode = NULL;
|
|
}
|
|
|
|
/*
|
|
* Is there a PRIV_DOORBELL pending for the guest (on POWER9)?
|
|
* Can we inject a Decrementer or a External interrupt?
|
|
*/
|
|
void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu)
|
|
{
|
|
int ext;
|
|
unsigned long vec = 0;
|
|
unsigned long lpcr;
|
|
|
|
/* Insert EXTERNAL bit into LPCR at the MER bit position */
|
|
ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1;
|
|
lpcr = mfspr(SPRN_LPCR);
|
|
lpcr |= ext << LPCR_MER_SH;
|
|
mtspr(SPRN_LPCR, lpcr);
|
|
isync();
|
|
|
|
if (vcpu->arch.shregs.msr & MSR_EE) {
|
|
if (ext) {
|
|
vec = BOOK3S_INTERRUPT_EXTERNAL;
|
|
} else {
|
|
long int dec = mfspr(SPRN_DEC);
|
|
if (!(lpcr & LPCR_LD))
|
|
dec = (int) dec;
|
|
if (dec < 0)
|
|
vec = BOOK3S_INTERRUPT_DECREMENTER;
|
|
}
|
|
}
|
|
if (vec) {
|
|
unsigned long msr, old_msr = vcpu->arch.shregs.msr;
|
|
|
|
kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu));
|
|
kvmppc_set_srr1(vcpu, old_msr);
|
|
kvmppc_set_pc(vcpu, vec);
|
|
msr = vcpu->arch.intr_msr;
|
|
if (MSR_TM_ACTIVE(old_msr))
|
|
msr |= MSR_TS_S;
|
|
vcpu->arch.shregs.msr = msr;
|
|
}
|
|
|
|
if (vcpu->arch.doorbell_request) {
|
|
mtspr(SPRN_DPDES, 1);
|
|
vcpu->arch.vcore->dpdes = 1;
|
|
smp_wmb();
|
|
vcpu->arch.doorbell_request = 0;
|
|
}
|
|
}
|
|
|
|
static void flush_guest_tlb(struct kvm *kvm)
|
|
{
|
|
unsigned long rb, set;
|
|
|
|
rb = PPC_BIT(52); /* IS = 2 */
|
|
if (kvm_is_radix(kvm)) {
|
|
/* R=1 PRS=1 RIC=2 */
|
|
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
|
|
: : "r" (rb), "i" (1), "i" (1), "i" (2),
|
|
"r" (0) : "memory");
|
|
for (set = 1; set < kvm->arch.tlb_sets; ++set) {
|
|
rb += PPC_BIT(51); /* increment set number */
|
|
/* R=1 PRS=1 RIC=0 */
|
|
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
|
|
: : "r" (rb), "i" (1), "i" (1), "i" (0),
|
|
"r" (0) : "memory");
|
|
}
|
|
asm volatile("ptesync": : :"memory");
|
|
asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory");
|
|
} else {
|
|
for (set = 0; set < kvm->arch.tlb_sets; ++set) {
|
|
/* R=0 PRS=0 RIC=0 */
|
|
asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
|
|
: : "r" (rb), "i" (0), "i" (0), "i" (0),
|
|
"r" (0) : "memory");
|
|
rb += PPC_BIT(51); /* increment set number */
|
|
}
|
|
asm volatile("ptesync": : :"memory");
|
|
asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory");
|
|
}
|
|
}
|
|
|
|
void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu,
|
|
struct kvm_nested_guest *nested)
|
|
{
|
|
cpumask_t *need_tlb_flush;
|
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/*
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* On POWER9, individual threads can come in here, but the
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* TLB is shared between the 4 threads in a core, hence
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* invalidating on one thread invalidates for all.
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* Thus we make all 4 threads use the same bit.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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pcpu = cpu_first_thread_sibling(pcpu);
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if (nested)
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need_tlb_flush = &nested->need_tlb_flush;
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else
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need_tlb_flush = &kvm->arch.need_tlb_flush;
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if (cpumask_test_cpu(pcpu, need_tlb_flush)) {
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flush_guest_tlb(kvm);
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/* Clear the bit after the TLB flush */
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cpumask_clear_cpu(pcpu, need_tlb_flush);
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}
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}
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EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush);
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