97d5c7a77e
Update the documentation about: 1. Usage of PMU_SPARE2 register. Bootloaders on Exynos542x-based boards often use the register PMU_SPARE2 (0x908) in the same way as on Exynos3250: as a indicator the secondary CPU was booted on. The bootloader will set this value to non-zero, after sucessfull power up of secondary CPU. In the same time this booted CPU will stuck (spin) waiting for software reset. 2. Exynos542x entry address for secondary CPU boot up after system suspend (with MCPM enabled and in non-secure mode). See arch/arm/mach-exynos/mcpm-exynos.c for source code. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
68 lines
3 KiB
Plaintext
68 lines
3 KiB
Plaintext
Interface between kernel and boot loaders on Exynos boards
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==========================================================
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Author: Krzysztof Kozlowski
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Date : 6 June 2015
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The document tries to describe currently used interface between Linux kernel
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and boot loaders on Samsung Exynos based boards. This is not a definition
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of interface but rather a description of existing state, a reference
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for information purpose only.
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In the document "boot loader" means any of following: U-boot, proprietary
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SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
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executing kernel.
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1. Non-Secure mode
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Address: sysram_ns_base_addr
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Offset Value Purpose
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=============================================================================
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0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
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0x0c 0x00000bad (Magic cookie) System suspend
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0x1c exynos4_secondary_startup Secondary CPU boot
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0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
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0x20 0xfcba0d10 (Magic cookie) AFTR
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0x24 exynos_cpu_resume_ns AFTR
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0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
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2. Secure mode
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Address: sysram_base_addr
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Offset Value Purpose
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=============================================================================
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0x00 exynos4_secondary_startup Secondary CPU boot
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0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
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4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
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0x20 exynos_cpu_resume (Exynos4210 r1.0) AFTR
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0x24 0xfcba0d10 (Magic cookie, Exynos4210 r1.0) AFTR
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Address: pmu_base_addr
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Offset Value Purpose
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=============================================================================
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0x0800 exynos_cpu_resume AFTR, suspend
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0x0800 mcpm_entry_point (Exynos542x with MCPM) AFTR, suspend
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0x0804 0xfcba0d10 (Magic cookie) AFTR
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0x0804 0x00000bad (Magic cookie) System suspend
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0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
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0x0818 0xfcba0d10 (Magic cookie, Exynos4210 r1.1) AFTR
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0x081C exynos_cpu_resume (Exynos4210 r1.1) AFTR
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3. Other (regardless of secure/non-secure mode)
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Address: pmu_base_addr
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Offset Value Purpose
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=============================================================================
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0x0908 Non-zero Secondary CPU boot up indicator
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on Exynos3250 and Exynos542x
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4. Glossary
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AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
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modules are power gated, except the TOP modules
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MCPM - Multi-Cluster Power Management
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