![Heiner Kallweit](/assets/img/avatar_default.png)
genphy_no_soft_reset and gen10g_no_soft_reset are both the same no-ops, one is enough. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
495 lines
12 KiB
C
495 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell 10G 88x3310 PHY driver
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*
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* Based upon the ID registers, this PHY appears to be a mixture of IPs
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* from two different companies.
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*
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* There appears to be several different data paths through the PHY which
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* are automatically managed by the PHY. The following has been determined
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* via observation and experimentation for a setup using single-lane Serdes:
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*
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* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
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* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
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* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
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*
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* With XAUI, observation shows:
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*
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* XAUI PHYXS -- <appropriate PCS as above>
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*
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* and no switching of the host interface mode occurs.
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*
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* If both the fiber and copper ports are connected, the first to gain
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* link takes priority and the other port is completely locked out.
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*/
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#include <linux/ctype.h>
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#include <linux/hwmon.h>
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#include <linux/marvell_phy.h>
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#include <linux/phy.h>
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#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
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#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
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enum {
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MV_PCS_BASE_T = 0x0000,
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MV_PCS_BASE_R = 0x1000,
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MV_PCS_1000BASEX = 0x2000,
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MV_PCS_PAIRSWAP = 0x8182,
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MV_PCS_PAIRSWAP_MASK = 0x0003,
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MV_PCS_PAIRSWAP_AB = 0x0002,
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MV_PCS_PAIRSWAP_NONE = 0x0003,
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/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
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* registers appear to set themselves to the 0x800X when AN is
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* restarted, but status registers appear readable from either.
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*/
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MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
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MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
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/* Vendor2 MMD registers */
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MV_V2_TEMP_CTRL = 0xf08a,
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MV_V2_TEMP_CTRL_MASK = 0xc000,
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MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
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MV_V2_TEMP_CTRL_DISABLE = 0xc000,
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MV_V2_TEMP = 0xf08c,
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MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
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};
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struct mv3310_priv {
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struct device *hwmon_dev;
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char *hwmon_name;
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};
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#ifdef CONFIG_HWMON
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static umode_t mv3310_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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if (type == hwmon_chip && attr == hwmon_chip_update_interval)
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return 0444;
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if (type == hwmon_temp && attr == hwmon_temp_input)
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return 0444;
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return 0;
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}
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static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *value)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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int temp;
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if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
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*value = MSEC_PER_SEC;
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return 0;
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}
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if (type == hwmon_temp && attr == hwmon_temp_input) {
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temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
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if (temp < 0)
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return temp;
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*value = ((temp & 0xff) - 75) * 1000;
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return 0;
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}
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return -EOPNOTSUPP;
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}
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static const struct hwmon_ops mv3310_hwmon_ops = {
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.is_visible = mv3310_hwmon_is_visible,
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.read = mv3310_hwmon_read,
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};
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static u32 mv3310_hwmon_chip_config[] = {
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HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
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0,
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};
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static const struct hwmon_channel_info mv3310_hwmon_chip = {
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.type = hwmon_chip,
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.config = mv3310_hwmon_chip_config,
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};
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static u32 mv3310_hwmon_temp_config[] = {
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HWMON_T_INPUT,
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0,
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};
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static const struct hwmon_channel_info mv3310_hwmon_temp = {
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.type = hwmon_temp,
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.config = mv3310_hwmon_temp_config,
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};
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static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
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&mv3310_hwmon_chip,
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&mv3310_hwmon_temp,
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NULL,
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};
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static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
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.ops = &mv3310_hwmon_ops,
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.info = mv3310_hwmon_info,
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};
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static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
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{
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u16 val;
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int ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
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MV_V2_TEMP_UNKNOWN);
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if (ret < 0)
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return ret;
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val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
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return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
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MV_V2_TEMP_CTRL_MASK, val);
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}
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static void mv3310_hwmon_disable(void *data)
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{
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struct phy_device *phydev = data;
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mv3310_hwmon_config(phydev, false);
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}
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static int mv3310_hwmon_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
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int i, j, ret;
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priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
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if (!priv->hwmon_name)
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return -ENODEV;
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for (i = j = 0; priv->hwmon_name[i]; i++) {
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if (isalnum(priv->hwmon_name[i])) {
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if (i != j)
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priv->hwmon_name[j] = priv->hwmon_name[i];
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j++;
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}
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}
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priv->hwmon_name[j] = '\0';
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ret = mv3310_hwmon_config(phydev, true);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
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if (ret)
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return ret;
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priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
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priv->hwmon_name, phydev,
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&mv3310_hwmon_chip_info, NULL);
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return PTR_ERR_OR_ZERO(priv->hwmon_dev);
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}
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#else
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static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
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{
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return 0;
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}
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static int mv3310_hwmon_probe(struct phy_device *phydev)
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{
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return 0;
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}
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#endif
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static int mv3310_probe(struct phy_device *phydev)
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{
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struct mv3310_priv *priv;
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u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
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int ret;
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if (!phydev->is_c45 ||
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(phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
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return -ENODEV;
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priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_set_drvdata(&phydev->mdio.dev, priv);
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ret = mv3310_hwmon_probe(phydev);
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if (ret)
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return ret;
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return 0;
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}
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static int mv3310_suspend(struct phy_device *phydev)
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{
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return 0;
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}
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static int mv3310_resume(struct phy_device *phydev)
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{
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return mv3310_hwmon_config(phydev, true);
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}
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/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
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* don't set bit 14 in PMA Extended Abilities (1.11), although they do
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* support 2.5GBASET and 5GBASET. For these models, we can still read their
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* 2.5G/5G extended abilities register (1.21). We detect these models based on
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* the PMA device identifier, with a mask matching models known to have this
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* issue
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*/
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static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
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{
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if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
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return false;
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/* Only some revisions of the 88X3310 family PMA seem to be impacted */
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return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
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MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
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}
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static int mv3310_config_init(struct phy_device *phydev)
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{
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/* Check that the PHY interface type is compatible */
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
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phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
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phydev->interface != PHY_INTERFACE_MODE_XAUI &&
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phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
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phydev->interface != PHY_INTERFACE_MODE_10GKR)
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return -ENODEV;
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return 0;
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}
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static int mv3310_get_features(struct phy_device *phydev)
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{
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int ret, val;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret)
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return ret;
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if (mv3310_has_pma_ngbaset_quirk(phydev)) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
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MDIO_PMA_NG_EXTABLE);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_2_5GBT);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_5GBT);
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}
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return 0;
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}
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static int mv3310_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u16 reg;
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int ret;
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/* We don't support manual MDI control */
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phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
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if (phydev->autoneg == AUTONEG_DISABLE)
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return genphy_c45_pma_setup_forced(phydev);
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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/* Clause 45 has no standardized support for 1000BaseT, therefore
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* use vendor registers for this mode.
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*/
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reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int mv3310_aneg_done(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_STAT1_LSTATUS)
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return 1;
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return genphy_c45_aneg_done(phydev);
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}
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static void mv3310_update_interface(struct phy_device *phydev)
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{
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if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
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phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
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phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
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/* The PHY automatically switches its serdes interface (and
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* active PHYXS instance) between Cisco SGMII, 10GBase-KR and
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* 2500BaseX modes according to the speed. Florian suggests
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* setting phydev->interface to communicate this to the MAC.
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* Only do this if we are already in one of the above modes.
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*/
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switch (phydev->speed) {
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case SPEED_10000:
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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break;
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case SPEED_2500:
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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break;
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case SPEED_1000:
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case SPEED_100:
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case SPEED_10:
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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break;
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default:
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break;
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}
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}
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}
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/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
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static int mv3310_read_10gbr_status(struct phy_device *phydev)
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{
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phydev->link = 1;
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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mv3310_update_interface(phydev);
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return 0;
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}
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static int mv3310_read_status(struct phy_device *phydev)
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{
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int val;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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linkmode_zero(phydev->lp_advertising);
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phydev->link = 0;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phydev->mdix = 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_STAT1_LSTATUS)
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return mv3310_read_10gbr_status(phydev);
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val = genphy_c45_read_link(phydev);
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if (val < 0)
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return val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_AN_STAT1_COMPLETE) {
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val = genphy_c45_read_lpa(phydev);
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if (val < 0)
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return val;
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/* Read the link partner's 1G advertisement */
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
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if (val < 0)
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return val;
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mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
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if (phydev->autoneg == AUTONEG_ENABLE)
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phy_resolve_aneg_linkmode(phydev);
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}
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if (phydev->autoneg != AUTONEG_ENABLE) {
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val = genphy_c45_read_pma(phydev);
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if (val < 0)
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return val;
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}
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if (phydev->speed == SPEED_10000) {
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val = genphy_c45_read_mdix(phydev);
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if (val < 0)
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return val;
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} else {
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
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if (val < 0)
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return val;
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switch (val & MV_PCS_PAIRSWAP_MASK) {
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case MV_PCS_PAIRSWAP_AB:
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phydev->mdix = ETH_TP_MDI_X;
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break;
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case MV_PCS_PAIRSWAP_NONE:
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phydev->mdix = ETH_TP_MDI;
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break;
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default:
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phydev->mdix = ETH_TP_MDI_INVALID;
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break;
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}
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}
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mv3310_update_interface(phydev);
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return 0;
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}
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static struct phy_driver mv3310_drivers[] = {
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{
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.phy_id = MARVELL_PHY_ID_88X3310,
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.phy_id_mask = MARVELL_PHY_ID_MASK,
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.name = "mv88x3310",
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.get_features = mv3310_get_features,
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.soft_reset = genphy_no_soft_reset,
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.config_init = mv3310_config_init,
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.probe = mv3310_probe,
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.suspend = mv3310_suspend,
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.resume = mv3310_resume,
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.config_aneg = mv3310_config_aneg,
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.aneg_done = mv3310_aneg_done,
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.read_status = mv3310_read_status,
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},
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{
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.phy_id = MARVELL_PHY_ID_88E2110,
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.phy_id_mask = MARVELL_PHY_ID_MASK,
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.name = "mv88x2110",
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.get_features = genphy_c45_pma_read_abilities,
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.probe = mv3310_probe,
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.soft_reset = genphy_no_soft_reset,
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.config_init = mv3310_config_init,
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.config_aneg = mv3310_config_aneg,
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.aneg_done = mv3310_aneg_done,
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.read_status = mv3310_read_status,
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},
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};
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module_phy_driver(mv3310_drivers);
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static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
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{ MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
|
|
{ MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
|
|
MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
|
|
MODULE_LICENSE("GPL");
|