![Andrew Lunn](/assets/img/avatar_default.png)
A few PHY drivers have the GPLv2+ license text. They then either have a MODULE_LICENSE() of GPLv2 only, or an SPDX tag of GPLv2 only. Since the license text is much easier to understand than either the SPDX tag or the MODULE_LICENSE, use it as the definitive source of the licence, and fixup the others when there are contradictions. Cc: David Wu <david.wu@rock-chips.com> Cc: Dongpo Li <lidongpo@hisilicon.com> Cc: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Michael Schmitz <schmitzmic@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
228 lines
4.9 KiB
C
228 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* drivers/net/phy/rockchip.c
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*
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* Driver for ROCKCHIP Ethernet PHYs
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*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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*
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* David Wu <david.wu@rock-chips.com>
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*/
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#include <linux/ethtool.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#define INTERNAL_EPHY_ID 0x1234d400
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#define MII_INTERNAL_CTRL_STATUS 17
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#define SMI_ADDR_TSTCNTL 20
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#define SMI_ADDR_TSTREAD1 21
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#define SMI_ADDR_TSTREAD2 22
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#define SMI_ADDR_TSTWRITE 23
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#define MII_SPECIAL_CONTROL_STATUS 31
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#define MII_AUTO_MDIX_EN BIT(7)
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#define MII_MDIX_EN BIT(6)
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#define MII_SPEED_10 BIT(2)
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#define MII_SPEED_100 BIT(3)
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#define TSTCNTL_RD (BIT(15) | BIT(10))
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#define TSTCNTL_WR (BIT(14) | BIT(10))
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#define TSTMODE_ENABLE 0x400
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#define TSTMODE_DISABLE 0x0
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#define WR_ADDR_A7CFG 0x18
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static int rockchip_init_tstmode(struct phy_device *phydev)
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{
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int ret;
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/* Enable access to Analog and DSP register banks */
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
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if (ret)
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return ret;
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
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if (ret)
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return ret;
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return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
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}
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static int rockchip_close_tstmode(struct phy_device *phydev)
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{
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/* Back to basic register bank */
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return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
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}
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static int rockchip_integrated_phy_analog_init(struct phy_device *phydev)
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{
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int ret;
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ret = rockchip_init_tstmode(phydev);
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if (ret)
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return ret;
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/*
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* Adjust tx amplitude to make sginal better,
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* the default value is 0x8.
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*/
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ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
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if (ret)
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return ret;
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ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
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if (ret)
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return ret;
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return rockchip_close_tstmode(phydev);
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}
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static int rockchip_integrated_phy_config_init(struct phy_device *phydev)
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{
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int val, ret;
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/*
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* The auto MIDX has linked problem on some board,
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* workround to disable auto MDIX.
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*/
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val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
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if (val < 0)
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return val;
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val &= ~MII_AUTO_MDIX_EN;
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ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
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if (ret)
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return ret;
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return rockchip_integrated_phy_analog_init(phydev);
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}
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static void rockchip_link_change_notify(struct phy_device *phydev)
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{
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int speed = SPEED_10;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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int reg = phy_read(phydev, MII_SPECIAL_CONTROL_STATUS);
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if (reg < 0) {
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phydev_err(phydev, "phy_read err: %d.\n", reg);
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return;
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}
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if (reg & MII_SPEED_100)
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speed = SPEED_100;
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else if (reg & MII_SPEED_10)
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speed = SPEED_10;
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} else {
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int bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0) {
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phydev_err(phydev, "phy_read err: %d.\n", bmcr);
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return;
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}
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if (bmcr & BMCR_SPEED100)
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speed = SPEED_100;
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else
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speed = SPEED_10;
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}
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/*
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* If mode switch happens from 10BT to 100BT, all DSP/AFE
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* registers are set to default values. So any AFE/DSP
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* registers have to be re-initialized in this case.
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*/
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if ((phydev->speed == SPEED_10) && (speed == SPEED_100)) {
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int ret = rockchip_integrated_phy_analog_init(phydev);
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if (ret)
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phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n",
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ret);
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}
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}
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static int rockchip_set_polarity(struct phy_device *phydev, int polarity)
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{
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int reg, err, val;
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/* get the current settings */
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reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
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if (reg < 0)
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return reg;
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reg &= ~MII_AUTO_MDIX_EN;
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val = reg;
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switch (polarity) {
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case ETH_TP_MDI:
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val &= ~MII_MDIX_EN;
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break;
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case ETH_TP_MDI_X:
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val |= MII_MDIX_EN;
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break;
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case ETH_TP_MDI_AUTO:
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case ETH_TP_MDI_INVALID:
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default:
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return 0;
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}
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if (val != reg) {
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/* Set the new polarity value in the register */
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err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
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if (err)
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return err;
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}
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return 0;
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}
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static int rockchip_config_aneg(struct phy_device *phydev)
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{
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int err;
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err = rockchip_set_polarity(phydev, phydev->mdix);
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if (err < 0)
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return err;
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return genphy_config_aneg(phydev);
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}
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static int rockchip_phy_resume(struct phy_device *phydev)
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{
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genphy_resume(phydev);
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return rockchip_integrated_phy_config_init(phydev);
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}
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static struct phy_driver rockchip_phy_driver[] = {
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{
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.phy_id = INTERNAL_EPHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "Rockchip integrated EPHY",
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.features = PHY_BASIC_FEATURES,
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.flags = 0,
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.link_change_notify = rockchip_link_change_notify,
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.soft_reset = genphy_soft_reset,
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.config_init = rockchip_integrated_phy_config_init,
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.config_aneg = rockchip_config_aneg,
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.suspend = genphy_suspend,
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.resume = rockchip_phy_resume,
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},
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};
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module_phy_driver(rockchip_phy_driver);
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static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
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{ INTERNAL_EPHY_ID, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
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MODULE_AUTHOR("David Wu <david.wu@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip Ethernet PHY driver");
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MODULE_LICENSE("GPL");
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