![Brian Norris](/assets/img/avatar_default.png)
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
441 lines
12 KiB
C
441 lines
12 KiB
C
/*
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* Calxeda Highbank AHCI SATA platform driver
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* Copyright 2012 Calxeda, Inc.
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/gfp.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/libata.h>
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#include <linux/ahci_platform.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include "ahci.h"
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#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
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#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
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#define SERDES_CR_CTL 0x80a0
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#define SERDES_CR_ADDR 0x80a1
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#define SERDES_CR_DATA 0x80a2
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#define CR_BUSY 0x0001
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#define CR_START 0x0001
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#define CR_WR_RDN 0x0002
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#define CPHY_RX_INPUT_STS 0x2002
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#define CPHY_SATA_OVERRIDE 0x4000
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#define CPHY_OVERRIDE 0x2005
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#define SPHY_LANE 0x100
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#define SPHY_HALF_RATE 0x0001
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#define CPHY_SATA_DPLL_MODE 0x0700
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#define CPHY_SATA_DPLL_SHIFT 8
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#define CPHY_SATA_DPLL_RESET (1 << 11)
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#define CPHY_PHY_COUNT 6
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#define CPHY_LANE_COUNT 4
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#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
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static DEFINE_SPINLOCK(cphy_lock);
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/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
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* sata ports to their phys and then to their lanes within the phys
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*/
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struct phy_lane_info {
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void __iomem *phy_base;
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u8 lane_mapping;
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u8 phy_devs;
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};
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static struct phy_lane_info port_data[CPHY_PORT_COUNT];
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static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
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{
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u32 data;
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u8 dev = port_data[sata_port].phy_devs;
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spin_lock(&cphy_lock);
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writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
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data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
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spin_unlock(&cphy_lock);
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return data;
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}
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static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
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{
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u8 dev = port_data[sata_port].phy_devs;
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spin_lock(&cphy_lock);
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writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
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writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
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spin_unlock(&cphy_lock);
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}
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static void combo_phy_wait_for_ready(u8 sata_port)
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{
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while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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}
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static u32 combo_phy_read(u8 sata_port, u32 addr)
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{
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combo_phy_wait_for_ready(sata_port);
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__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
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combo_phy_wait_for_ready(sata_port);
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return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
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}
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static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
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{
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combo_phy_wait_for_ready(sata_port);
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__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
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__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
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}
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static void highbank_cphy_disable_overrides(u8 sata_port)
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{
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u8 lane = port_data[sata_port].lane_mapping;
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u32 tmp;
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if (unlikely(port_data[sata_port].phy_base == NULL))
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return;
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_OVERRIDE;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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static void cphy_override_rx_mode(u8 sata_port, u32 val)
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{
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u8 lane = port_data[sata_port].lane_mapping;
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u32 tmp;
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_OVERRIDE;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_OVERRIDE;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp &= ~CPHY_SATA_DPLL_MODE;
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tmp |= val << CPHY_SATA_DPLL_SHIFT;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_DPLL_RESET;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp &= ~CPHY_SATA_DPLL_RESET;
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combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
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msleep(15);
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}
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static void highbank_cphy_override_lane(u8 sata_port)
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{
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u8 lane = port_data[sata_port].lane_mapping;
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u32 tmp, k = 0;
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if (unlikely(port_data[sata_port].phy_base == NULL))
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return;
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do {
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
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lane * SPHY_LANE);
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} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
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cphy_override_rx_mode(sata_port, 3);
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}
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static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
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{
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struct device_node *sata_node = dev->of_node;
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int phy_count = 0, phy, port = 0;
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void __iomem *cphy_base[CPHY_PHY_COUNT];
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struct device_node *phy_nodes[CPHY_PHY_COUNT];
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memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
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memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);
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do {
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u32 tmp;
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struct of_phandle_args phy_data;
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if (of_parse_phandle_with_args(sata_node,
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"calxeda,port-phys", "#phy-cells",
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port, &phy_data))
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break;
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for (phy = 0; phy < phy_count; phy++) {
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if (phy_nodes[phy] == phy_data.np)
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break;
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}
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if (phy_nodes[phy] == NULL) {
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phy_nodes[phy] = phy_data.np;
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cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
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if (cphy_base[phy] == NULL) {
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return 0;
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}
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phy_count += 1;
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}
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port_data[port].lane_mapping = phy_data.args[0];
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of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
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port_data[port].phy_devs = tmp;
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port_data[port].phy_base = cphy_base[phy];
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of_node_put(phy_data.np);
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port += 1;
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} while (port < CPHY_PORT_COUNT);
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return 0;
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}
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static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
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struct ata_port *ap = link->ap;
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struct ahci_port_priv *pp = ap->private_data;
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
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struct ata_taskfile tf;
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bool online;
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u32 sstatus;
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int rc;
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int retry = 10;
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ahci_stop_engine(ap);
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/* clear D2H reception area to properly wait for D2H FIS */
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ata_tf_init(link->device, &tf);
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tf.command = ATA_BUSY;
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ata_tf_to_fis(&tf, 0, 0, d2h_fis);
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do {
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highbank_cphy_disable_overrides(link->ap->port_no);
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rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
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highbank_cphy_override_lane(link->ap->port_no);
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/* If the status is 1, we are connected, but the link did not
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* come up. So retry resetting the link again.
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*/
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if (sata_scr_read(link, SCR_STATUS, &sstatus))
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break;
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if (!(sstatus & 0x3))
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break;
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} while (!online && retry--);
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ahci_start_engine(ap);
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if (online)
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*class = ahci_dev_classify(ap);
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return rc;
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}
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static struct ata_port_operations ahci_highbank_ops = {
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.inherits = &ahci_ops,
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.hardreset = ahci_highbank_hardreset,
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};
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static const struct ata_port_info ahci_highbank_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_highbank_ops,
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};
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static struct scsi_host_template ahci_highbank_platform_sht = {
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AHCI_SHT("highbank-ahci"),
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};
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static const struct of_device_id ahci_of_match[] = {
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{ .compatible = "calxeda,hb-ahci" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_of_match);
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static int __devinit ahci_highbank_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ata_host *host;
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struct resource *mem;
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int irq;
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int n_ports;
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int i;
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int rc;
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struct ata_port_info pi = ahci_highbank_port_info;
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const struct ata_port_info *ppi[] = { &pi, NULL };
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(dev, "no mmio space\n");
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return -EINVAL;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0) {
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dev_err(dev, "no irq\n");
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return -EINVAL;
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}
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hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
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if (!hpriv) {
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dev_err(dev, "can't alloc ahci_host_priv\n");
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return -ENOMEM;
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}
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hpriv->flags |= (unsigned long)pi.private_data;
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hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
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if (!hpriv->mmio) {
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dev_err(dev, "can't map %pR\n", mem);
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return -ENOMEM;
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}
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rc = highbank_initialize_phys(dev, hpriv->mmio);
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if (rc)
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return rc;
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ahci_save_initial_config(dev, hpriv, 0, 0);
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/* prepare host */
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if (hpriv->cap & HOST_CAP_NCQ)
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pi.flags |= ATA_FLAG_NCQ;
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if (hpriv->cap & HOST_CAP_PMP)
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pi.flags |= ATA_FLAG_PMP;
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ahci_set_em_messages(hpriv, &pi);
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/* CAP.NP sometimes indicate the index of the last enabled
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* port, at other times, that of the last possible port, so
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* determining the maximum port number requires looking at
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* both CAP.NP and port_map.
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*/
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n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
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host = ata_host_alloc_pinfo(dev, ppi, n_ports);
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if (!host) {
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rc = -ENOMEM;
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goto err0;
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}
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host->private_data = hpriv;
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if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
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host->flags |= ATA_HOST_PARALLEL_SCAN;
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if (pi.flags & ATA_FLAG_EM)
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ahci_reset_em(host);
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for (i = 0; i < host->n_ports; i++) {
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struct ata_port *ap = host->ports[i];
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ata_port_desc(ap, "mmio %pR", mem);
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ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
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/* set enclosure management message type */
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if (ap->flags & ATA_FLAG_EM)
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ap->em_message_type = hpriv->em_msg_type;
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/* disabled/not-implemented port */
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if (!(hpriv->port_map & (1 << i)))
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ap->ops = &ata_dummy_port_ops;
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}
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rc = ahci_reset_controller(host);
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if (rc)
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goto err0;
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ahci_init_controller(host);
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ahci_print_info(host, "platform");
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rc = ata_host_activate(host, irq, ahci_interrupt, 0,
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&ahci_highbank_platform_sht);
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if (rc)
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goto err0;
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return 0;
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err0:
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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static int ahci_highbank_suspend(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->mmio;
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u32 ctl;
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int rc;
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if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
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dev_err(dev, "firmware update required for suspend/resume\n");
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return -EIO;
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}
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/*
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* AHCI spec rev1.1 section 8.3.3:
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* Software must disable interrupts prior to requesting a
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* transition of the HBA to D3 state.
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*/
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ctl = readl(mmio + HOST_CTL);
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ctl &= ~HOST_IRQ_EN;
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writel(ctl, mmio + HOST_CTL);
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readl(mmio + HOST_CTL); /* flush */
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rc = ata_host_suspend(host, PMSG_SUSPEND);
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if (rc)
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return rc;
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return 0;
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}
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static int ahci_highbank_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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int rc;
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if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
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rc = ahci_reset_controller(host);
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if (rc)
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return rc;
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ahci_init_controller(host);
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}
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ata_host_resume(host);
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return 0;
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}
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#endif
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SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
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ahci_highbank_suspend, ahci_highbank_resume);
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static struct platform_driver ahci_highbank_driver = {
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.remove = ata_platform_remove_one,
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.driver = {
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.name = "highbank-ahci",
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.owner = THIS_MODULE,
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.of_match_table = ahci_of_match,
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.pm = &ahci_highbank_pm_ops,
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},
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.probe = ahci_highbank_probe,
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};
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module_platform_driver(ahci_highbank_driver);
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MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
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MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("sata:highbank");
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