![Stephan Gerhold](/assets/img/avatar_default.png)
So far we have been doing all proxy votes by voting for raw voltages/load through the regulator interface. But actually VDDCX and VDDMX represent power domains that should be preferably managed using corner votes through the power domain interface. Looking closer the code was actually never doing the proxy votes correctly: The vddcx regulator is specified as: { "vddcx", .super_turbo = true }, which is supposed to say that we should vote for the maximum corner of the VDDCX power domain. But actually "super_turbo" is unused so all we did so far is to enable the power domain. We did not vote for it to scale to the maximum performance state. Using them through the power domain interface allows voting for the maximum performance state. However, we still need to support using them through the regulator interface for old device trees. The way this is implemented here is that we check if attaching the two power domain succeeds. If yes, we skip the first "num_pd_vregs" regulators in the "vregs" list and only request the remaining ones. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200916104135.25085-9-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
709 lines
16 KiB
C
709 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
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*
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* Copyright (C) 2016 Linaro Ltd
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* Copyright (C) 2014 Sony Mobile Communications AB
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/qcom_scm.h>
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#include <linux/regulator/consumer.h>
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#include <linux/remoteproc.h>
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#include <linux/soc/qcom/mdt_loader.h>
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#include <linux/soc/qcom/smem.h>
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#include <linux/soc/qcom/smem_state.h>
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#include <linux/rpmsg/qcom_smd.h>
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#include "qcom_common.h"
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#include "remoteproc_internal.h"
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#include "qcom_pil_info.h"
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#include "qcom_wcnss.h"
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#define WCNSS_CRASH_REASON_SMEM 422
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#define WCNSS_FIRMWARE_NAME "wcnss.mdt"
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#define WCNSS_PAS_ID 6
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#define WCNSS_SSCTL_ID 0x13
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#define WCNSS_SPARE_NVBIN_DLND BIT(25)
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#define WCNSS_PMU_IRIS_XO_CFG BIT(3)
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#define WCNSS_PMU_IRIS_XO_EN BIT(4)
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#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
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#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
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#define WCNSS_PMU_IRIS_RESET BIT(7)
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#define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
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#define WCNSS_PMU_IRIS_XO_READ BIT(9)
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#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
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#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
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#define WCNSS_PMU_XO_MODE_19p2 0
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#define WCNSS_PMU_XO_MODE_48 3
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#define WCNSS_MAX_PDS 2
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struct wcnss_data {
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size_t pmu_offset;
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size_t spare_offset;
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const char *pd_names[WCNSS_MAX_PDS];
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const struct wcnss_vreg_info *vregs;
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size_t num_vregs, num_pd_vregs;
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};
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struct qcom_wcnss {
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struct device *dev;
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struct rproc *rproc;
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void __iomem *pmu_cfg;
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void __iomem *spare_out;
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bool use_48mhz_xo;
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int wdog_irq;
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int fatal_irq;
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int ready_irq;
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int handover_irq;
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int stop_ack_irq;
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struct qcom_smem_state *state;
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unsigned stop_bit;
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struct mutex iris_lock;
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struct qcom_iris *iris;
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struct device *pds[WCNSS_MAX_PDS];
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size_t num_pds;
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struct regulator_bulk_data *vregs;
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size_t num_vregs;
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struct completion start_done;
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struct completion stop_done;
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phys_addr_t mem_phys;
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phys_addr_t mem_reloc;
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void *mem_region;
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size_t mem_size;
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struct qcom_rproc_subdev smd_subdev;
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struct qcom_sysmon *sysmon;
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};
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static const struct wcnss_data riva_data = {
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.pmu_offset = 0x28,
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.spare_offset = 0xb4,
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.vregs = (struct wcnss_vreg_info[]) {
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{ "vddmx", 1050000, 1150000, 0 },
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{ "vddcx", 1050000, 1150000, 0 },
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{ "vddpx", 1800000, 1800000, 0 },
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},
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.num_vregs = 3,
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};
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static const struct wcnss_data pronto_v1_data = {
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.pmu_offset = 0x1004,
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.spare_offset = 0x1088,
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.pd_names = { "mx", "cx" },
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.vregs = (struct wcnss_vreg_info[]) {
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{ "vddmx", 950000, 1150000, 0 },
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{ "vddcx", .super_turbo = true},
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{ "vddpx", 1800000, 1800000, 0 },
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},
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.num_pd_vregs = 2,
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.num_vregs = 1,
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};
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static const struct wcnss_data pronto_v2_data = {
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.pmu_offset = 0x1004,
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.spare_offset = 0x1088,
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.pd_names = { "mx", "cx" },
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.vregs = (struct wcnss_vreg_info[]) {
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{ "vddmx", 1287500, 1287500, 0 },
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{ "vddcx", .super_turbo = true },
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{ "vddpx", 1800000, 1800000, 0 },
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},
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.num_pd_vregs = 2,
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.num_vregs = 1,
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};
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void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
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struct qcom_iris *iris,
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bool use_48mhz_xo)
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{
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mutex_lock(&wcnss->iris_lock);
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wcnss->iris = iris;
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wcnss->use_48mhz_xo = use_48mhz_xo;
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mutex_unlock(&wcnss->iris_lock);
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}
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static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
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{
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
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int ret;
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ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
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wcnss->mem_region, wcnss->mem_phys,
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wcnss->mem_size, &wcnss->mem_reloc);
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if (ret)
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return ret;
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qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
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return 0;
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}
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static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
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{
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u32 val;
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/* Indicate NV download capability */
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val = readl(wcnss->spare_out);
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val |= WCNSS_SPARE_NVBIN_DLND;
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writel(val, wcnss->spare_out);
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}
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static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
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{
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u32 val;
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/* Clear PMU cfg register */
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writel(0, wcnss->pmu_cfg);
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val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
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writel(val, wcnss->pmu_cfg);
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/* Clear XO_MODE */
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val &= ~WCNSS_PMU_XO_MODE_MASK;
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if (wcnss->use_48mhz_xo)
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val |= WCNSS_PMU_XO_MODE_48 << 1;
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else
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val |= WCNSS_PMU_XO_MODE_19p2 << 1;
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writel(val, wcnss->pmu_cfg);
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/* Reset IRIS */
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val |= WCNSS_PMU_IRIS_RESET;
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writel(val, wcnss->pmu_cfg);
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/* Wait for PMU.iris_reg_reset_sts */
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while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
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cpu_relax();
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/* Clear IRIS reset */
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val &= ~WCNSS_PMU_IRIS_RESET;
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writel(val, wcnss->pmu_cfg);
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/* Start IRIS XO configuration */
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val |= WCNSS_PMU_IRIS_XO_CFG;
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writel(val, wcnss->pmu_cfg);
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/* Wait for XO configuration to finish */
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while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
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cpu_relax();
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/* Stop IRIS XO configuration */
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val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
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val &= ~WCNSS_PMU_IRIS_XO_CFG;
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writel(val, wcnss->pmu_cfg);
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/* Add some delay for XO to settle */
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msleep(20);
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}
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static int wcnss_start(struct rproc *rproc)
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{
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
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int ret, i;
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mutex_lock(&wcnss->iris_lock);
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if (!wcnss->iris) {
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dev_err(wcnss->dev, "no iris registered\n");
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ret = -EINVAL;
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goto release_iris_lock;
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}
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for (i = 0; i < wcnss->num_pds; i++) {
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dev_pm_genpd_set_performance_state(wcnss->pds[i], INT_MAX);
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ret = pm_runtime_get_sync(wcnss->pds[i]);
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if (ret < 0) {
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pm_runtime_put_noidle(wcnss->pds[i]);
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goto disable_pds;
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}
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}
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ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
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if (ret)
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goto disable_pds;
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ret = qcom_iris_enable(wcnss->iris);
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if (ret)
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goto disable_regulators;
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wcnss_indicate_nv_download(wcnss);
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wcnss_configure_iris(wcnss);
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ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
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if (ret) {
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dev_err(wcnss->dev,
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"failed to authenticate image and release reset\n");
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goto disable_iris;
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}
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ret = wait_for_completion_timeout(&wcnss->start_done,
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msecs_to_jiffies(5000));
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if (wcnss->ready_irq > 0 && ret == 0) {
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/* We have a ready_irq, but it didn't fire in time. */
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dev_err(wcnss->dev, "start timed out\n");
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qcom_scm_pas_shutdown(WCNSS_PAS_ID);
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ret = -ETIMEDOUT;
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goto disable_iris;
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}
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ret = 0;
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disable_iris:
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qcom_iris_disable(wcnss->iris);
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disable_regulators:
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regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
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disable_pds:
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for (i--; i >= 0; i--) {
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pm_runtime_put(wcnss->pds[i]);
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dev_pm_genpd_set_performance_state(wcnss->pds[i], 0);
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}
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release_iris_lock:
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mutex_unlock(&wcnss->iris_lock);
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return ret;
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}
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static int wcnss_stop(struct rproc *rproc)
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{
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
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int ret;
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if (wcnss->state) {
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qcom_smem_state_update_bits(wcnss->state,
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BIT(wcnss->stop_bit),
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BIT(wcnss->stop_bit));
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ret = wait_for_completion_timeout(&wcnss->stop_done,
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msecs_to_jiffies(5000));
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if (ret == 0)
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dev_err(wcnss->dev, "timed out on wait\n");
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qcom_smem_state_update_bits(wcnss->state,
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BIT(wcnss->stop_bit),
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0);
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}
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ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
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if (ret)
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dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
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return ret;
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}
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static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len)
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{
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struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
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int offset;
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offset = da - wcnss->mem_reloc;
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if (offset < 0 || offset + len > wcnss->mem_size)
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return NULL;
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return wcnss->mem_region + offset;
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}
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static const struct rproc_ops wcnss_ops = {
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.start = wcnss_start,
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.stop = wcnss_stop,
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.da_to_va = wcnss_da_to_va,
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.parse_fw = qcom_register_dump_segments,
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.load = wcnss_load,
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};
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static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
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{
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struct qcom_wcnss *wcnss = dev;
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rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
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return IRQ_HANDLED;
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}
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static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
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{
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struct qcom_wcnss *wcnss = dev;
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size_t len;
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char *msg;
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msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
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if (!IS_ERR(msg) && len > 0 && msg[0])
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dev_err(wcnss->dev, "fatal error received: %s\n", msg);
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rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
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return IRQ_HANDLED;
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}
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static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
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{
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struct qcom_wcnss *wcnss = dev;
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complete(&wcnss->start_done);
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return IRQ_HANDLED;
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}
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static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
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{
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/*
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* XXX: At this point we're supposed to release the resources that we
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* have been holding on behalf of the WCNSS. Unfortunately this
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* interrupt comes way before the other side seems to be done.
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*
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* So we're currently relying on the ready interrupt firing later then
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* this and we just disable the resources at the end of wcnss_start().
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*/
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return IRQ_HANDLED;
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}
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static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
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{
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struct qcom_wcnss *wcnss = dev;
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complete(&wcnss->stop_done);
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return IRQ_HANDLED;
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}
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static int wcnss_init_pds(struct qcom_wcnss *wcnss,
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const char * const pd_names[WCNSS_MAX_PDS])
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{
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int i, ret;
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for (i = 0; i < WCNSS_MAX_PDS; i++) {
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if (!pd_names[i])
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break;
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wcnss->pds[i] = dev_pm_domain_attach_by_name(wcnss->dev, pd_names[i]);
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if (IS_ERR_OR_NULL(wcnss->pds[i])) {
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ret = PTR_ERR(wcnss->pds[i]) ? : -ENODATA;
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for (i--; i >= 0; i--)
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dev_pm_domain_detach(wcnss->pds[i], false);
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return ret;
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}
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}
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wcnss->num_pds = i;
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return 0;
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}
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static void wcnss_release_pds(struct qcom_wcnss *wcnss)
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{
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int i;
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for (i = 0; i < wcnss->num_pds; i++)
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dev_pm_domain_detach(wcnss->pds[i], false);
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}
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static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
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const struct wcnss_vreg_info *info,
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int num_vregs, int num_pd_vregs)
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{
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struct regulator_bulk_data *bulk;
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int ret;
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int i;
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/*
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* If attaching the power domains suceeded we can skip requesting
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* the regulators for the power domains. For old device trees we need to
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* reserve extra space to manage them through the regulator interface.
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*/
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if (wcnss->num_pds)
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info += num_pd_vregs;
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else
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num_vregs += num_pd_vregs;
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bulk = devm_kcalloc(wcnss->dev,
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num_vregs, sizeof(struct regulator_bulk_data),
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GFP_KERNEL);
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if (!bulk)
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return -ENOMEM;
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for (i = 0; i < num_vregs; i++)
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bulk[i].supply = info[i].name;
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ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
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if (ret)
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return ret;
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for (i = 0; i < num_vregs; i++) {
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if (info[i].max_voltage)
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regulator_set_voltage(bulk[i].consumer,
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info[i].min_voltage,
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info[i].max_voltage);
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if (info[i].load_uA)
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regulator_set_load(bulk[i].consumer, info[i].load_uA);
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}
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wcnss->vregs = bulk;
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wcnss->num_vregs = num_vregs;
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return 0;
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}
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static int wcnss_request_irq(struct qcom_wcnss *wcnss,
|
|
struct platform_device *pdev,
|
|
const char *name,
|
|
bool optional,
|
|
irq_handler_t thread_fn)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_get_irq_byname(pdev, name);
|
|
if (ret < 0 && optional) {
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|
dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
|
|
return 0;
|
|
} else if (ret < 0) {
|
|
dev_err(&pdev->dev, "no %s IRQ defined\n", name);
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, ret,
|
|
NULL, thread_fn,
|
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IRQF_TRIGGER_RISING | IRQF_ONESHOT,
|
|
"wcnss", wcnss);
|
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if (ret)
|
|
dev_err(&pdev->dev, "request %s IRQ failed\n", name);
|
|
|
|
return ret;
|
|
}
|
|
|
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static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
|
|
{
|
|
struct device_node *node;
|
|
struct resource r;
|
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int ret;
|
|
|
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node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
|
|
if (!node) {
|
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dev_err(wcnss->dev, "no memory-region specified\n");
|
|
return -EINVAL;
|
|
}
|
|
|
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ret = of_address_to_resource(node, 0, &r);
|
|
if (ret)
|
|
return ret;
|
|
|
|
wcnss->mem_phys = wcnss->mem_reloc = r.start;
|
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wcnss->mem_size = resource_size(&r);
|
|
wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
|
|
if (!wcnss->mem_region) {
|
|
dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
|
|
&r.start, wcnss->mem_size);
|
|
return -EBUSY;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int wcnss_probe(struct platform_device *pdev)
|
|
{
|
|
const struct wcnss_data *data;
|
|
struct qcom_wcnss *wcnss;
|
|
struct resource *res;
|
|
struct rproc *rproc;
|
|
void __iomem *mmio;
|
|
int ret;
|
|
|
|
data = of_device_get_match_data(&pdev->dev);
|
|
|
|
if (!qcom_scm_is_available())
|
|
return -EPROBE_DEFER;
|
|
|
|
if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
|
|
dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
|
|
WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
|
|
if (!rproc) {
|
|
dev_err(&pdev->dev, "unable to allocate remoteproc\n");
|
|
return -ENOMEM;
|
|
}
|
|
rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
|
|
|
|
wcnss = (struct qcom_wcnss *)rproc->priv;
|
|
wcnss->dev = &pdev->dev;
|
|
wcnss->rproc = rproc;
|
|
platform_set_drvdata(pdev, wcnss);
|
|
|
|
init_completion(&wcnss->start_done);
|
|
init_completion(&wcnss->stop_done);
|
|
|
|
mutex_init(&wcnss->iris_lock);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
|
|
mmio = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(mmio)) {
|
|
ret = PTR_ERR(mmio);
|
|
goto free_rproc;
|
|
};
|
|
|
|
ret = wcnss_alloc_memory_region(wcnss);
|
|
if (ret)
|
|
goto free_rproc;
|
|
|
|
wcnss->pmu_cfg = mmio + data->pmu_offset;
|
|
wcnss->spare_out = mmio + data->spare_offset;
|
|
|
|
/*
|
|
* We might need to fallback to regulators instead of power domains
|
|
* for old device trees. Don't report an error in that case.
|
|
*/
|
|
ret = wcnss_init_pds(wcnss, data->pd_names);
|
|
if (ret && (ret != -ENODATA || !data->num_pd_vregs))
|
|
goto free_rproc;
|
|
|
|
ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs,
|
|
data->num_pd_vregs);
|
|
if (ret)
|
|
goto detach_pds;
|
|
|
|
ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
|
|
if (ret < 0)
|
|
goto detach_pds;
|
|
wcnss->wdog_irq = ret;
|
|
|
|
ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
|
|
if (ret < 0)
|
|
goto detach_pds;
|
|
wcnss->fatal_irq = ret;
|
|
|
|
ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
|
|
if (ret < 0)
|
|
goto detach_pds;
|
|
wcnss->ready_irq = ret;
|
|
|
|
ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
|
|
if (ret < 0)
|
|
goto detach_pds;
|
|
wcnss->handover_irq = ret;
|
|
|
|
ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
|
|
if (ret < 0)
|
|
goto detach_pds;
|
|
wcnss->stop_ack_irq = ret;
|
|
|
|
if (wcnss->stop_ack_irq) {
|
|
wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
|
|
&wcnss->stop_bit);
|
|
if (IS_ERR(wcnss->state)) {
|
|
ret = PTR_ERR(wcnss->state);
|
|
goto detach_pds;
|
|
}
|
|
}
|
|
|
|
qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
|
|
wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
|
|
if (IS_ERR(wcnss->sysmon)) {
|
|
ret = PTR_ERR(wcnss->sysmon);
|
|
goto detach_pds;
|
|
}
|
|
|
|
ret = rproc_add(rproc);
|
|
if (ret)
|
|
goto detach_pds;
|
|
|
|
return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
|
|
|
detach_pds:
|
|
wcnss_release_pds(wcnss);
|
|
free_rproc:
|
|
rproc_free(rproc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int wcnss_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
|
|
|
|
of_platform_depopulate(&pdev->dev);
|
|
|
|
qcom_smem_state_put(wcnss->state);
|
|
rproc_del(wcnss->rproc);
|
|
|
|
qcom_remove_sysmon_subdev(wcnss->sysmon);
|
|
qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
|
|
wcnss_release_pds(wcnss);
|
|
rproc_free(wcnss->rproc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id wcnss_of_match[] = {
|
|
{ .compatible = "qcom,riva-pil", &riva_data },
|
|
{ .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
|
|
{ .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, wcnss_of_match);
|
|
|
|
static struct platform_driver wcnss_driver = {
|
|
.probe = wcnss_probe,
|
|
.remove = wcnss_remove,
|
|
.driver = {
|
|
.name = "qcom-wcnss-pil",
|
|
.of_match_table = wcnss_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init wcnss_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&wcnss_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&qcom_iris_driver);
|
|
if (ret)
|
|
platform_driver_unregister(&wcnss_driver);
|
|
|
|
return ret;
|
|
}
|
|
module_init(wcnss_init);
|
|
|
|
static void __exit wcnss_exit(void)
|
|
{
|
|
platform_driver_unregister(&qcom_iris_driver);
|
|
platform_driver_unregister(&wcnss_driver);
|
|
}
|
|
module_exit(wcnss_exit);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
|
|
MODULE_LICENSE("GPL v2");
|