![Randy Dunlap](/assets/img/avatar_default.png)
At over 4000 #includes, <linux/platform_device.h> is the 9th most #included header file in the Linux kernel. It does not need <linux/mod_devicetable.h>, so drop that header and explicitly add <linux/mod_devicetable.h> to source files that need it. 4146 #include <linux/platform_device.h> After this patch, there are 225 files that use <linux/mod_devicetable.h>, for a reduction of around 3900 times that <linux/mod_devicetable.h> does not have to be read & parsed. 225 #include <linux/mod_devicetable.h> This patch was build-tested on 20 different arch-es. It also makes these drivers SubmitChecklist#1 compliant. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kbuild test robot <lkp@intel.com> # drivers/media/platform/vimc/ Reported-by: kbuild test robot <lkp@intel.com> # drivers/pinctrl/pinctrl-u300.c Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1419 lines
38 KiB
C
1419 lines
38 KiB
C
/*
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* Driver for the Cirrus Logic EP93xx DMA Controller
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*
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* Copyright (C) 2011 Mika Westerberg
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*
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* DMA M2P implementation is based on the original
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* arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright (C) 2006 Applied Data Systems
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* Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
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*
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* This driver is based on dw_dmac and amba-pl08x drivers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include "dmaengine.h"
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/* M2P registers */
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#define M2P_CONTROL 0x0000
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#define M2P_CONTROL_STALLINT BIT(0)
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#define M2P_CONTROL_NFBINT BIT(1)
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#define M2P_CONTROL_CH_ERROR_INT BIT(3)
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#define M2P_CONTROL_ENABLE BIT(4)
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#define M2P_CONTROL_ICE BIT(6)
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#define M2P_INTERRUPT 0x0004
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#define M2P_INTERRUPT_STALL BIT(0)
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#define M2P_INTERRUPT_NFB BIT(1)
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#define M2P_INTERRUPT_ERROR BIT(3)
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#define M2P_PPALLOC 0x0008
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#define M2P_STATUS 0x000c
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#define M2P_MAXCNT0 0x0020
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#define M2P_BASE0 0x0024
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#define M2P_MAXCNT1 0x0030
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#define M2P_BASE1 0x0034
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#define M2P_STATE_IDLE 0
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#define M2P_STATE_STALL 1
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#define M2P_STATE_ON 2
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#define M2P_STATE_NEXT 3
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/* M2M registers */
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#define M2M_CONTROL 0x0000
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#define M2M_CONTROL_DONEINT BIT(2)
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#define M2M_CONTROL_ENABLE BIT(3)
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#define M2M_CONTROL_START BIT(4)
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#define M2M_CONTROL_DAH BIT(11)
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#define M2M_CONTROL_SAH BIT(12)
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#define M2M_CONTROL_PW_SHIFT 9
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#define M2M_CONTROL_PW_8 (0 << M2M_CONTROL_PW_SHIFT)
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#define M2M_CONTROL_PW_16 (1 << M2M_CONTROL_PW_SHIFT)
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#define M2M_CONTROL_PW_32 (2 << M2M_CONTROL_PW_SHIFT)
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#define M2M_CONTROL_PW_MASK (3 << M2M_CONTROL_PW_SHIFT)
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#define M2M_CONTROL_TM_SHIFT 13
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#define M2M_CONTROL_TM_TX (1 << M2M_CONTROL_TM_SHIFT)
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#define M2M_CONTROL_TM_RX (2 << M2M_CONTROL_TM_SHIFT)
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#define M2M_CONTROL_NFBINT BIT(21)
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#define M2M_CONTROL_RSS_SHIFT 22
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#define M2M_CONTROL_RSS_SSPRX (1 << M2M_CONTROL_RSS_SHIFT)
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#define M2M_CONTROL_RSS_SSPTX (2 << M2M_CONTROL_RSS_SHIFT)
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#define M2M_CONTROL_RSS_IDE (3 << M2M_CONTROL_RSS_SHIFT)
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#define M2M_CONTROL_NO_HDSK BIT(24)
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#define M2M_CONTROL_PWSC_SHIFT 25
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#define M2M_INTERRUPT 0x0004
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#define M2M_INTERRUPT_MASK 6
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#define M2M_STATUS 0x000c
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#define M2M_STATUS_CTL_SHIFT 1
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#define M2M_STATUS_CTL_IDLE (0 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_CTL_STALL (1 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_CTL_MEMRD (2 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_CTL_MEMWR (3 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_CTL_BWCWAIT (4 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_CTL_MASK (7 << M2M_STATUS_CTL_SHIFT)
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#define M2M_STATUS_BUF_SHIFT 4
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#define M2M_STATUS_BUF_NO (0 << M2M_STATUS_BUF_SHIFT)
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#define M2M_STATUS_BUF_ON (1 << M2M_STATUS_BUF_SHIFT)
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#define M2M_STATUS_BUF_NEXT (2 << M2M_STATUS_BUF_SHIFT)
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#define M2M_STATUS_BUF_MASK (3 << M2M_STATUS_BUF_SHIFT)
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#define M2M_STATUS_DONE BIT(6)
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#define M2M_BCR0 0x0010
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#define M2M_BCR1 0x0014
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#define M2M_SAR_BASE0 0x0018
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#define M2M_SAR_BASE1 0x001c
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#define M2M_DAR_BASE0 0x002c
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#define M2M_DAR_BASE1 0x0030
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#define DMA_MAX_CHAN_BYTES 0xffff
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#define DMA_MAX_CHAN_DESCRIPTORS 32
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struct ep93xx_dma_engine;
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/**
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* struct ep93xx_dma_desc - EP93xx specific transaction descriptor
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* @src_addr: source address of the transaction
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* @dst_addr: destination address of the transaction
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* @size: size of the transaction (in bytes)
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* @complete: this descriptor is completed
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* @txd: dmaengine API descriptor
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* @tx_list: list of linked descriptors
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* @node: link used for putting this into a channel queue
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*/
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struct ep93xx_dma_desc {
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u32 src_addr;
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u32 dst_addr;
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size_t size;
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bool complete;
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struct dma_async_tx_descriptor txd;
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struct list_head tx_list;
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struct list_head node;
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};
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/**
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* struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
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* @chan: dmaengine API channel
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* @edma: pointer to to the engine device
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* @regs: memory mapped registers
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* @irq: interrupt number of the channel
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* @clk: clock used by this channel
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* @tasklet: channel specific tasklet used for callbacks
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* @lock: lock protecting the fields following
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* @flags: flags for the channel
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* @buffer: which buffer to use next (0/1)
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* @active: flattened chain of descriptors currently being processed
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* @queue: pending descriptors which are handled next
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* @free_list: list of free descriptors which can be used
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* @runtime_addr: physical address currently used as dest/src (M2M only). This
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* is set via .device_config before slave operation is
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* prepared
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* @runtime_ctrl: M2M runtime values for the control register.
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*
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* As EP93xx DMA controller doesn't support real chained DMA descriptors we
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* will have slightly different scheme here: @active points to a head of
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* flattened DMA descriptor chain.
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*
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* @queue holds pending transactions. These are linked through the first
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* descriptor in the chain. When a descriptor is moved to the @active queue,
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* the first and chained descriptors are flattened into a single list.
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*
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* @chan.private holds pointer to &struct ep93xx_dma_data which contains
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* necessary channel configuration information. For memcpy channels this must
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* be %NULL.
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*/
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struct ep93xx_dma_chan {
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struct dma_chan chan;
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const struct ep93xx_dma_engine *edma;
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void __iomem *regs;
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int irq;
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struct clk *clk;
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struct tasklet_struct tasklet;
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/* protects the fields following */
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spinlock_t lock;
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unsigned long flags;
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/* Channel is configured for cyclic transfers */
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#define EP93XX_DMA_IS_CYCLIC 0
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int buffer;
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struct list_head active;
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struct list_head queue;
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struct list_head free_list;
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u32 runtime_addr;
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u32 runtime_ctrl;
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};
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/**
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* struct ep93xx_dma_engine - the EP93xx DMA engine instance
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* @dma_dev: holds the dmaengine device
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* @m2m: is this an M2M or M2P device
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* @hw_setup: method which sets the channel up for operation
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* @hw_shutdown: shuts the channel down and flushes whatever is left
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* @hw_submit: pushes active descriptor(s) to the hardware
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* @hw_interrupt: handle the interrupt
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* @num_channels: number of channels for this instance
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* @channels: array of channels
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*
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* There is one instance of this struct for the M2P channels and one for the
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* M2M channels. hw_xxx() methods are used to perform operations which are
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* different on M2M and M2P channels. These methods are called with channel
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* lock held and interrupts disabled so they cannot sleep.
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*/
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struct ep93xx_dma_engine {
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struct dma_device dma_dev;
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bool m2m;
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int (*hw_setup)(struct ep93xx_dma_chan *);
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void (*hw_synchronize)(struct ep93xx_dma_chan *);
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void (*hw_shutdown)(struct ep93xx_dma_chan *);
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void (*hw_submit)(struct ep93xx_dma_chan *);
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int (*hw_interrupt)(struct ep93xx_dma_chan *);
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#define INTERRUPT_UNKNOWN 0
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#define INTERRUPT_DONE 1
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#define INTERRUPT_NEXT_BUFFER 2
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size_t num_channels;
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struct ep93xx_dma_chan channels[];
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};
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static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)
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{
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return &edmac->chan.dev->device;
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}
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static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct ep93xx_dma_chan, chan);
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}
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/**
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* ep93xx_dma_set_active - set new active descriptor chain
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* @edmac: channel
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* @desc: head of the new active descriptor chain
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*
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* Sets @desc to be the head of the new active descriptor chain. This is the
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* chain which is processed next. The active list must be empty before calling
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* this function.
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*
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* Called with @edmac->lock held and interrupts disabled.
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*/
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static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
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struct ep93xx_dma_desc *desc)
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{
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BUG_ON(!list_empty(&edmac->active));
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list_add_tail(&desc->node, &edmac->active);
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/* Flatten the @desc->tx_list chain into @edmac->active list */
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while (!list_empty(&desc->tx_list)) {
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struct ep93xx_dma_desc *d = list_first_entry(&desc->tx_list,
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struct ep93xx_dma_desc, node);
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/*
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* We copy the callback parameters from the first descriptor
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* to all the chained descriptors. This way we can call the
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* callback without having to find out the first descriptor in
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* the chain. Useful for cyclic transfers.
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*/
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d->txd.callback = desc->txd.callback;
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d->txd.callback_param = desc->txd.callback_param;
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list_move_tail(&d->node, &edmac->active);
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}
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}
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/* Called with @edmac->lock held and interrupts disabled */
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static struct ep93xx_dma_desc *
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ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
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{
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return list_first_entry_or_null(&edmac->active,
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struct ep93xx_dma_desc, node);
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}
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/**
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* ep93xx_dma_advance_active - advances to the next active descriptor
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* @edmac: channel
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*
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* Function advances active descriptor to the next in the @edmac->active and
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* returns %true if we still have descriptors in the chain to process.
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* Otherwise returns %false.
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*
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* When the channel is in cyclic mode always returns %true.
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*
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* Called with @edmac->lock held and interrupts disabled.
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*/
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static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)
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{
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struct ep93xx_dma_desc *desc;
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list_rotate_left(&edmac->active);
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if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
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return true;
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desc = ep93xx_dma_get_active(edmac);
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if (!desc)
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return false;
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/*
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* If txd.cookie is set it means that we are back in the first
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* descriptor in the chain and hence done with it.
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*/
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return !desc->txd.cookie;
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}
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/*
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* M2P DMA implementation
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*/
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static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control)
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{
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writel(control, edmac->regs + M2P_CONTROL);
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/*
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* EP93xx User's Guide states that we must perform a dummy read after
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* write to the control register.
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*/
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readl(edmac->regs + M2P_CONTROL);
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}
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static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)
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{
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struct ep93xx_dma_data *data = edmac->chan.private;
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u32 control;
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writel(data->port & 0xf, edmac->regs + M2P_PPALLOC);
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control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE
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| M2P_CONTROL_ENABLE;
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m2p_set_control(edmac, control);
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edmac->buffer = 0;
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return 0;
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}
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static inline u32 m2p_channel_state(struct ep93xx_dma_chan *edmac)
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{
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return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;
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}
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static void m2p_hw_synchronize(struct ep93xx_dma_chan *edmac)
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{
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unsigned long flags;
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u32 control;
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spin_lock_irqsave(&edmac->lock, flags);
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control = readl(edmac->regs + M2P_CONTROL);
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control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
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m2p_set_control(edmac, control);
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spin_unlock_irqrestore(&edmac->lock, flags);
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while (m2p_channel_state(edmac) >= M2P_STATE_ON)
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schedule();
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}
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static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
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{
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m2p_set_control(edmac, 0);
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while (m2p_channel_state(edmac) != M2P_STATE_IDLE)
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dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n");
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}
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static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
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{
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struct ep93xx_dma_desc *desc;
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u32 bus_addr;
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desc = ep93xx_dma_get_active(edmac);
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if (!desc) {
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dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n");
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return;
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}
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if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
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bus_addr = desc->src_addr;
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else
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bus_addr = desc->dst_addr;
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if (edmac->buffer == 0) {
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writel(desc->size, edmac->regs + M2P_MAXCNT0);
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writel(bus_addr, edmac->regs + M2P_BASE0);
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} else {
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writel(desc->size, edmac->regs + M2P_MAXCNT1);
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writel(bus_addr, edmac->regs + M2P_BASE1);
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}
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edmac->buffer ^= 1;
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}
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static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)
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{
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u32 control = readl(edmac->regs + M2P_CONTROL);
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m2p_fill_desc(edmac);
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control |= M2P_CONTROL_STALLINT;
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if (ep93xx_dma_advance_active(edmac)) {
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m2p_fill_desc(edmac);
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control |= M2P_CONTROL_NFBINT;
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}
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m2p_set_control(edmac, control);
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}
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static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
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{
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u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);
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u32 control;
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if (irq_status & M2P_INTERRUPT_ERROR) {
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struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
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/* Clear the error interrupt */
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writel(1, edmac->regs + M2P_INTERRUPT);
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/*
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* It seems that there is no easy way of reporting errors back
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* to client so we just report the error here and continue as
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* usual.
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*
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* Revisit this when there is a mechanism to report back the
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* errors.
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*/
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dev_err(chan2dev(edmac),
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"DMA transfer failed! Details:\n"
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"\tcookie : %d\n"
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"\tsrc_addr : 0x%08x\n"
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"\tdst_addr : 0x%08x\n"
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"\tsize : %zu\n",
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desc->txd.cookie, desc->src_addr, desc->dst_addr,
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desc->size);
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}
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/*
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* Even latest E2 silicon revision sometimes assert STALL interrupt
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* instead of NFB. Therefore we treat them equally, basing on the
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* amount of data we still have to transfer.
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*/
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if (!(irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)))
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return INTERRUPT_UNKNOWN;
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if (ep93xx_dma_advance_active(edmac)) {
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m2p_fill_desc(edmac);
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return INTERRUPT_NEXT_BUFFER;
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}
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/* Disable interrupts */
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control = readl(edmac->regs + M2P_CONTROL);
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control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
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m2p_set_control(edmac, control);
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return INTERRUPT_DONE;
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}
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/*
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* M2M DMA implementation
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*/
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static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
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{
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|
const struct ep93xx_dma_data *data = edmac->chan.private;
|
|
u32 control = 0;
|
|
|
|
if (!data) {
|
|
/* This is memcpy channel, nothing to configure */
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
switch (data->port) {
|
|
case EP93XX_DMA_SSP:
|
|
/*
|
|
* This was found via experimenting - anything less than 5
|
|
* causes the channel to perform only a partial transfer which
|
|
* leads to problems since we don't get DONE interrupt then.
|
|
*/
|
|
control = (5 << M2M_CONTROL_PWSC_SHIFT);
|
|
control |= M2M_CONTROL_NO_HDSK;
|
|
|
|
if (data->direction == DMA_MEM_TO_DEV) {
|
|
control |= M2M_CONTROL_DAH;
|
|
control |= M2M_CONTROL_TM_TX;
|
|
control |= M2M_CONTROL_RSS_SSPTX;
|
|
} else {
|
|
control |= M2M_CONTROL_SAH;
|
|
control |= M2M_CONTROL_TM_RX;
|
|
control |= M2M_CONTROL_RSS_SSPRX;
|
|
}
|
|
break;
|
|
|
|
case EP93XX_DMA_IDE:
|
|
/*
|
|
* This IDE part is totally untested. Values below are taken
|
|
* from the EP93xx Users's Guide and might not be correct.
|
|
*/
|
|
if (data->direction == DMA_MEM_TO_DEV) {
|
|
/* Worst case from the UG */
|
|
control = (3 << M2M_CONTROL_PWSC_SHIFT);
|
|
control |= M2M_CONTROL_DAH;
|
|
control |= M2M_CONTROL_TM_TX;
|
|
} else {
|
|
control = (2 << M2M_CONTROL_PWSC_SHIFT);
|
|
control |= M2M_CONTROL_SAH;
|
|
control |= M2M_CONTROL_TM_RX;
|
|
}
|
|
|
|
control |= M2M_CONTROL_NO_HDSK;
|
|
control |= M2M_CONTROL_RSS_IDE;
|
|
control |= M2M_CONTROL_PW_16;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
/* Just disable the channel */
|
|
writel(0, edmac->regs + M2M_CONTROL);
|
|
}
|
|
|
|
static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
struct ep93xx_dma_desc *desc;
|
|
|
|
desc = ep93xx_dma_get_active(edmac);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n");
|
|
return;
|
|
}
|
|
|
|
if (edmac->buffer == 0) {
|
|
writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
|
|
writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
|
|
writel(desc->size, edmac->regs + M2M_BCR0);
|
|
} else {
|
|
writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
|
|
writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
|
|
writel(desc->size, edmac->regs + M2M_BCR1);
|
|
}
|
|
|
|
edmac->buffer ^= 1;
|
|
}
|
|
|
|
static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
struct ep93xx_dma_data *data = edmac->chan.private;
|
|
u32 control = readl(edmac->regs + M2M_CONTROL);
|
|
|
|
/*
|
|
* Since we allow clients to configure PW (peripheral width) we always
|
|
* clear PW bits here and then set them according what is given in
|
|
* the runtime configuration.
|
|
*/
|
|
control &= ~M2M_CONTROL_PW_MASK;
|
|
control |= edmac->runtime_ctrl;
|
|
|
|
m2m_fill_desc(edmac);
|
|
control |= M2M_CONTROL_DONEINT;
|
|
|
|
if (ep93xx_dma_advance_active(edmac)) {
|
|
m2m_fill_desc(edmac);
|
|
control |= M2M_CONTROL_NFBINT;
|
|
}
|
|
|
|
/*
|
|
* Now we can finally enable the channel. For M2M channel this must be
|
|
* done _after_ the BCRx registers are programmed.
|
|
*/
|
|
control |= M2M_CONTROL_ENABLE;
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
|
|
if (!data) {
|
|
/*
|
|
* For memcpy channels the software trigger must be asserted
|
|
* in order to start the memcpy operation.
|
|
*/
|
|
control |= M2M_CONTROL_START;
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* According to EP93xx User's Guide, we should receive DONE interrupt when all
|
|
* M2M DMA controller transactions complete normally. This is not always the
|
|
* case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel
|
|
* is still running (channel Buffer FSM in DMA_BUF_ON state, and channel
|
|
* Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).
|
|
* In effect, disabling the channel when only DONE bit is set could stop
|
|
* currently running DMA transfer. To avoid this, we use Buffer FSM and
|
|
* Control FSM to check current state of DMA channel.
|
|
*/
|
|
static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
u32 status = readl(edmac->regs + M2M_STATUS);
|
|
u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;
|
|
u32 buf_fsm = status & M2M_STATUS_BUF_MASK;
|
|
bool done = status & M2M_STATUS_DONE;
|
|
bool last_done;
|
|
u32 control;
|
|
struct ep93xx_dma_desc *desc;
|
|
|
|
/* Accept only DONE and NFB interrupts */
|
|
if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
|
|
return INTERRUPT_UNKNOWN;
|
|
|
|
if (done) {
|
|
/* Clear the DONE bit */
|
|
writel(0, edmac->regs + M2M_INTERRUPT);
|
|
}
|
|
|
|
/*
|
|
* Check whether we are done with descriptors or not. This, together
|
|
* with DMA channel state, determines action to take in interrupt.
|
|
*/
|
|
desc = ep93xx_dma_get_active(edmac);
|
|
last_done = !desc || desc->txd.cookie;
|
|
|
|
/*
|
|
* Use M2M DMA Buffer FSM and Control FSM to check current state of
|
|
* DMA channel. Using DONE and NFB bits from channel status register
|
|
* or bits from channel interrupt register is not reliable.
|
|
*/
|
|
if (!last_done &&
|
|
(buf_fsm == M2M_STATUS_BUF_NO ||
|
|
buf_fsm == M2M_STATUS_BUF_ON)) {
|
|
/*
|
|
* Two buffers are ready for update when Buffer FSM is in
|
|
* DMA_NO_BUF state. Only one buffer can be prepared without
|
|
* disabling the channel or polling the DONE bit.
|
|
* To simplify things, always prepare only one buffer.
|
|
*/
|
|
if (ep93xx_dma_advance_active(edmac)) {
|
|
m2m_fill_desc(edmac);
|
|
if (done && !edmac->chan.private) {
|
|
/* Software trigger for memcpy channel */
|
|
control = readl(edmac->regs + M2M_CONTROL);
|
|
control |= M2M_CONTROL_START;
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
}
|
|
return INTERRUPT_NEXT_BUFFER;
|
|
} else {
|
|
last_done = true;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Disable the channel only when Buffer FSM is in DMA_NO_BUF state
|
|
* and Control FSM is in DMA_STALL state.
|
|
*/
|
|
if (last_done &&
|
|
buf_fsm == M2M_STATUS_BUF_NO &&
|
|
ctl_fsm == M2M_STATUS_CTL_STALL) {
|
|
/* Disable interrupts and the channel */
|
|
control = readl(edmac->regs + M2M_CONTROL);
|
|
control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT
|
|
| M2M_CONTROL_ENABLE);
|
|
writel(control, edmac->regs + M2M_CONTROL);
|
|
return INTERRUPT_DONE;
|
|
}
|
|
|
|
/*
|
|
* Nothing to do this time.
|
|
*/
|
|
return INTERRUPT_NEXT_BUFFER;
|
|
}
|
|
|
|
/*
|
|
* DMA engine API implementation
|
|
*/
|
|
|
|
static struct ep93xx_dma_desc *
|
|
ep93xx_dma_desc_get(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
struct ep93xx_dma_desc *desc, *_desc;
|
|
struct ep93xx_dma_desc *ret = NULL;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {
|
|
if (async_tx_test_ack(&desc->txd)) {
|
|
list_del_init(&desc->node);
|
|
|
|
/* Re-initialize the descriptor */
|
|
desc->src_addr = 0;
|
|
desc->dst_addr = 0;
|
|
desc->size = 0;
|
|
desc->complete = false;
|
|
desc->txd.cookie = 0;
|
|
desc->txd.callback = NULL;
|
|
desc->txd.callback_param = NULL;
|
|
|
|
ret = desc;
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static void ep93xx_dma_desc_put(struct ep93xx_dma_chan *edmac,
|
|
struct ep93xx_dma_desc *desc)
|
|
{
|
|
if (desc) {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
list_splice_init(&desc->tx_list, &edmac->free_list);
|
|
list_add(&desc->node, &edmac->free_list);
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_advance_work - start processing the next pending transaction
|
|
* @edmac: channel
|
|
*
|
|
* If we have pending transactions queued and we are currently idling, this
|
|
* function takes the next queued transaction from the @edmac->queue and
|
|
* pushes it to the hardware for execution.
|
|
*/
|
|
static void ep93xx_dma_advance_work(struct ep93xx_dma_chan *edmac)
|
|
{
|
|
struct ep93xx_dma_desc *new;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
if (!list_empty(&edmac->active) || list_empty(&edmac->queue)) {
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
return;
|
|
}
|
|
|
|
/* Take the next descriptor from the pending queue */
|
|
new = list_first_entry(&edmac->queue, struct ep93xx_dma_desc, node);
|
|
list_del_init(&new->node);
|
|
|
|
ep93xx_dma_set_active(edmac, new);
|
|
|
|
/* Push it to the hardware */
|
|
edmac->edma->hw_submit(edmac);
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
}
|
|
|
|
static void ep93xx_dma_tasklet(unsigned long data)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = (struct ep93xx_dma_chan *)data;
|
|
struct ep93xx_dma_desc *desc, *d;
|
|
struct dmaengine_desc_callback cb;
|
|
LIST_HEAD(list);
|
|
|
|
memset(&cb, 0, sizeof(cb));
|
|
spin_lock_irq(&edmac->lock);
|
|
/*
|
|
* If dma_terminate_all() was called before we get to run, the active
|
|
* list has become empty. If that happens we aren't supposed to do
|
|
* anything more than call ep93xx_dma_advance_work().
|
|
*/
|
|
desc = ep93xx_dma_get_active(edmac);
|
|
if (desc) {
|
|
if (desc->complete) {
|
|
/* mark descriptor complete for non cyclic case only */
|
|
if (!test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
|
|
dma_cookie_complete(&desc->txd);
|
|
list_splice_init(&edmac->active, &list);
|
|
}
|
|
dmaengine_desc_get_callback(&desc->txd, &cb);
|
|
}
|
|
spin_unlock_irq(&edmac->lock);
|
|
|
|
/* Pick up the next descriptor from the queue */
|
|
ep93xx_dma_advance_work(edmac);
|
|
|
|
/* Now we can release all the chained descriptors */
|
|
list_for_each_entry_safe(desc, d, &list, node) {
|
|
dma_descriptor_unmap(&desc->txd);
|
|
ep93xx_dma_desc_put(edmac, desc);
|
|
}
|
|
|
|
dmaengine_desc_callback_invoke(&cb, NULL);
|
|
}
|
|
|
|
static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = dev_id;
|
|
struct ep93xx_dma_desc *desc;
|
|
irqreturn_t ret = IRQ_HANDLED;
|
|
|
|
spin_lock(&edmac->lock);
|
|
|
|
desc = ep93xx_dma_get_active(edmac);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac),
|
|
"got interrupt while active list is empty\n");
|
|
spin_unlock(&edmac->lock);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
switch (edmac->edma->hw_interrupt(edmac)) {
|
|
case INTERRUPT_DONE:
|
|
desc->complete = true;
|
|
tasklet_schedule(&edmac->tasklet);
|
|
break;
|
|
|
|
case INTERRUPT_NEXT_BUFFER:
|
|
if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
|
|
tasklet_schedule(&edmac->tasklet);
|
|
break;
|
|
|
|
default:
|
|
dev_warn(chan2dev(edmac), "unknown interrupt!\n");
|
|
ret = IRQ_NONE;
|
|
break;
|
|
}
|
|
|
|
spin_unlock(&edmac->lock);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_tx_submit - set the prepared descriptor(s) to be executed
|
|
* @tx: descriptor to be executed
|
|
*
|
|
* Function will execute given descriptor on the hardware or if the hardware
|
|
* is busy, queue the descriptor to be executed later on. Returns cookie which
|
|
* can be used to poll the status of the descriptor.
|
|
*/
|
|
static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(tx->chan);
|
|
struct ep93xx_dma_desc *desc;
|
|
dma_cookie_t cookie;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
cookie = dma_cookie_assign(tx);
|
|
|
|
desc = container_of(tx, struct ep93xx_dma_desc, txd);
|
|
|
|
/*
|
|
* If nothing is currently prosessed, we push this descriptor
|
|
* directly to the hardware. Otherwise we put the descriptor
|
|
* to the pending queue.
|
|
*/
|
|
if (list_empty(&edmac->active)) {
|
|
ep93xx_dma_set_active(edmac, desc);
|
|
edmac->edma->hw_submit(edmac);
|
|
} else {
|
|
list_add_tail(&desc->node, &edmac->queue);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
return cookie;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_alloc_chan_resources - allocate resources for the channel
|
|
* @chan: channel to allocate resources
|
|
*
|
|
* Function allocates necessary resources for the given DMA channel and
|
|
* returns number of allocated descriptors for the channel. Negative errno
|
|
* is returned in case of failure.
|
|
*/
|
|
static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_data *data = chan->private;
|
|
const char *name = dma_chan_name(chan);
|
|
int ret, i;
|
|
|
|
/* Sanity check the channel parameters */
|
|
if (!edmac->edma->m2m) {
|
|
if (!data)
|
|
return -EINVAL;
|
|
if (data->port < EP93XX_DMA_I2S1 ||
|
|
data->port > EP93XX_DMA_IRDA)
|
|
return -EINVAL;
|
|
if (data->direction != ep93xx_dma_chan_direction(chan))
|
|
return -EINVAL;
|
|
} else {
|
|
if (data) {
|
|
switch (data->port) {
|
|
case EP93XX_DMA_SSP:
|
|
case EP93XX_DMA_IDE:
|
|
if (!is_slave_direction(data->direction))
|
|
return -EINVAL;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (data && data->name)
|
|
name = data->name;
|
|
|
|
ret = clk_enable(edmac->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = request_irq(edmac->irq, ep93xx_dma_interrupt, 0, name, edmac);
|
|
if (ret)
|
|
goto fail_clk_disable;
|
|
|
|
spin_lock_irq(&edmac->lock);
|
|
dma_cookie_init(&edmac->chan);
|
|
ret = edmac->edma->hw_setup(edmac);
|
|
spin_unlock_irq(&edmac->lock);
|
|
|
|
if (ret)
|
|
goto fail_free_irq;
|
|
|
|
for (i = 0; i < DMA_MAX_CHAN_DESCRIPTORS; i++) {
|
|
struct ep93xx_dma_desc *desc;
|
|
|
|
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac), "not enough descriptors\n");
|
|
break;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&desc->tx_list);
|
|
|
|
dma_async_tx_descriptor_init(&desc->txd, chan);
|
|
desc->txd.flags = DMA_CTRL_ACK;
|
|
desc->txd.tx_submit = ep93xx_dma_tx_submit;
|
|
|
|
ep93xx_dma_desc_put(edmac, desc);
|
|
}
|
|
|
|
return i;
|
|
|
|
fail_free_irq:
|
|
free_irq(edmac->irq, edmac);
|
|
fail_clk_disable:
|
|
clk_disable(edmac->clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_free_chan_resources - release resources for the channel
|
|
* @chan: channel
|
|
*
|
|
* Function releases all the resources allocated for the given channel.
|
|
* The channel must be idle when this is called.
|
|
*/
|
|
static void ep93xx_dma_free_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_desc *desc, *d;
|
|
unsigned long flags;
|
|
LIST_HEAD(list);
|
|
|
|
BUG_ON(!list_empty(&edmac->active));
|
|
BUG_ON(!list_empty(&edmac->queue));
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
edmac->edma->hw_shutdown(edmac);
|
|
edmac->runtime_addr = 0;
|
|
edmac->runtime_ctrl = 0;
|
|
edmac->buffer = 0;
|
|
list_splice_init(&edmac->free_list, &list);
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
|
|
list_for_each_entry_safe(desc, d, &list, node)
|
|
kfree(desc);
|
|
|
|
clk_disable(edmac->clk);
|
|
free_irq(edmac->irq, edmac);
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_prep_dma_memcpy - prepare a memcpy DMA operation
|
|
* @chan: channel
|
|
* @dest: destination bus address
|
|
* @src: source bus address
|
|
* @len: size of the transaction
|
|
* @flags: flags for the descriptor
|
|
*
|
|
* Returns a valid DMA descriptor or %NULL in case of failure.
|
|
*/
|
|
static struct dma_async_tx_descriptor *
|
|
ep93xx_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
|
|
dma_addr_t src, size_t len, unsigned long flags)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_desc *desc, *first;
|
|
size_t bytes, offset;
|
|
|
|
first = NULL;
|
|
for (offset = 0; offset < len; offset += bytes) {
|
|
desc = ep93xx_dma_desc_get(edmac);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac), "couln't get descriptor\n");
|
|
goto fail;
|
|
}
|
|
|
|
bytes = min_t(size_t, len - offset, DMA_MAX_CHAN_BYTES);
|
|
|
|
desc->src_addr = src + offset;
|
|
desc->dst_addr = dest + offset;
|
|
desc->size = bytes;
|
|
|
|
if (!first)
|
|
first = desc;
|
|
else
|
|
list_add_tail(&desc->node, &first->tx_list);
|
|
}
|
|
|
|
first->txd.cookie = -EBUSY;
|
|
first->txd.flags = flags;
|
|
|
|
return &first->txd;
|
|
fail:
|
|
ep93xx_dma_desc_put(edmac, first);
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_prep_slave_sg - prepare a slave DMA operation
|
|
* @chan: channel
|
|
* @sgl: list of buffers to transfer
|
|
* @sg_len: number of entries in @sgl
|
|
* @dir: direction of tha DMA transfer
|
|
* @flags: flags for the descriptor
|
|
* @context: operation context (ignored)
|
|
*
|
|
* Returns a valid DMA descriptor or %NULL in case of failure.
|
|
*/
|
|
static struct dma_async_tx_descriptor *
|
|
ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction dir,
|
|
unsigned long flags, void *context)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_desc *desc, *first;
|
|
struct scatterlist *sg;
|
|
int i;
|
|
|
|
if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
|
|
dev_warn(chan2dev(edmac),
|
|
"channel was configured with different direction\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
|
|
dev_warn(chan2dev(edmac),
|
|
"channel is already used for cyclic transfers\n");
|
|
return NULL;
|
|
}
|
|
|
|
first = NULL;
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
size_t len = sg_dma_len(sg);
|
|
|
|
if (len > DMA_MAX_CHAN_BYTES) {
|
|
dev_warn(chan2dev(edmac), "too big transfer size %zu\n",
|
|
len);
|
|
goto fail;
|
|
}
|
|
|
|
desc = ep93xx_dma_desc_get(edmac);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac), "couln't get descriptor\n");
|
|
goto fail;
|
|
}
|
|
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
desc->src_addr = sg_dma_address(sg);
|
|
desc->dst_addr = edmac->runtime_addr;
|
|
} else {
|
|
desc->src_addr = edmac->runtime_addr;
|
|
desc->dst_addr = sg_dma_address(sg);
|
|
}
|
|
desc->size = len;
|
|
|
|
if (!first)
|
|
first = desc;
|
|
else
|
|
list_add_tail(&desc->node, &first->tx_list);
|
|
}
|
|
|
|
first->txd.cookie = -EBUSY;
|
|
first->txd.flags = flags;
|
|
|
|
return &first->txd;
|
|
|
|
fail:
|
|
ep93xx_dma_desc_put(edmac, first);
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_prep_dma_cyclic - prepare a cyclic DMA operation
|
|
* @chan: channel
|
|
* @dma_addr: DMA mapped address of the buffer
|
|
* @buf_len: length of the buffer (in bytes)
|
|
* @period_len: length of a single period
|
|
* @dir: direction of the operation
|
|
* @flags: tx descriptor status flags
|
|
*
|
|
* Prepares a descriptor for cyclic DMA operation. This means that once the
|
|
* descriptor is submitted, we will be submitting in a @period_len sized
|
|
* buffers and calling callback once the period has been elapsed. Transfer
|
|
* terminates only when client calls dmaengine_terminate_all() for this
|
|
* channel.
|
|
*
|
|
* Returns a valid DMA descriptor or %NULL in case of failure.
|
|
*/
|
|
static struct dma_async_tx_descriptor *
|
|
ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
|
|
size_t buf_len, size_t period_len,
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_desc *desc, *first;
|
|
size_t offset = 0;
|
|
|
|
if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
|
|
dev_warn(chan2dev(edmac),
|
|
"channel was configured with different direction\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
|
|
dev_warn(chan2dev(edmac),
|
|
"channel is already used for cyclic transfers\n");
|
|
return NULL;
|
|
}
|
|
|
|
if (period_len > DMA_MAX_CHAN_BYTES) {
|
|
dev_warn(chan2dev(edmac), "too big period length %zu\n",
|
|
period_len);
|
|
return NULL;
|
|
}
|
|
|
|
/* Split the buffer into period size chunks */
|
|
first = NULL;
|
|
for (offset = 0; offset < buf_len; offset += period_len) {
|
|
desc = ep93xx_dma_desc_get(edmac);
|
|
if (!desc) {
|
|
dev_warn(chan2dev(edmac), "couln't get descriptor\n");
|
|
goto fail;
|
|
}
|
|
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
desc->src_addr = dma_addr + offset;
|
|
desc->dst_addr = edmac->runtime_addr;
|
|
} else {
|
|
desc->src_addr = edmac->runtime_addr;
|
|
desc->dst_addr = dma_addr + offset;
|
|
}
|
|
|
|
desc->size = period_len;
|
|
|
|
if (!first)
|
|
first = desc;
|
|
else
|
|
list_add_tail(&desc->node, &first->tx_list);
|
|
}
|
|
|
|
first->txd.cookie = -EBUSY;
|
|
|
|
return &first->txd;
|
|
|
|
fail:
|
|
ep93xx_dma_desc_put(edmac, first);
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_synchronize - Synchronizes the termination of transfers to the
|
|
* current context.
|
|
* @chan: channel
|
|
*
|
|
* Synchronizes the DMA channel termination to the current context. When this
|
|
* function returns it is guaranteed that all transfers for previously issued
|
|
* descriptors have stopped and and it is safe to free the memory associated
|
|
* with them. Furthermore it is guaranteed that all complete callback functions
|
|
* for a previously submitted descriptor have finished running and it is safe to
|
|
* free resources accessed from within the complete callbacks.
|
|
*/
|
|
static void ep93xx_dma_synchronize(struct dma_chan *chan)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
|
|
if (edmac->edma->hw_synchronize)
|
|
edmac->edma->hw_synchronize(edmac);
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_terminate_all - terminate all transactions
|
|
* @chan: channel
|
|
*
|
|
* Stops all DMA transactions. All descriptors are put back to the
|
|
* @edmac->free_list and callbacks are _not_ called.
|
|
*/
|
|
static int ep93xx_dma_terminate_all(struct dma_chan *chan)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
struct ep93xx_dma_desc *desc, *_d;
|
|
unsigned long flags;
|
|
LIST_HEAD(list);
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
/* First we disable and flush the DMA channel */
|
|
edmac->edma->hw_shutdown(edmac);
|
|
clear_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags);
|
|
list_splice_init(&edmac->active, &list);
|
|
list_splice_init(&edmac->queue, &list);
|
|
/*
|
|
* We then re-enable the channel. This way we can continue submitting
|
|
* the descriptors by just calling ->hw_submit() again.
|
|
*/
|
|
edmac->edma->hw_setup(edmac);
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
|
|
list_for_each_entry_safe(desc, _d, &list, node)
|
|
ep93xx_dma_desc_put(edmac, desc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ep93xx_dma_slave_config(struct dma_chan *chan,
|
|
struct dma_slave_config *config)
|
|
{
|
|
struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
|
|
enum dma_slave_buswidth width;
|
|
unsigned long flags;
|
|
u32 addr, ctrl;
|
|
|
|
if (!edmac->edma->m2m)
|
|
return -EINVAL;
|
|
|
|
switch (config->direction) {
|
|
case DMA_DEV_TO_MEM:
|
|
width = config->src_addr_width;
|
|
addr = config->src_addr;
|
|
break;
|
|
|
|
case DMA_MEM_TO_DEV:
|
|
width = config->dst_addr_width;
|
|
addr = config->dst_addr;
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (width) {
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
ctrl = 0;
|
|
break;
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
ctrl = M2M_CONTROL_PW_16;
|
|
break;
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
ctrl = M2M_CONTROL_PW_32;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&edmac->lock, flags);
|
|
edmac->runtime_addr = addr;
|
|
edmac->runtime_ctrl = ctrl;
|
|
spin_unlock_irqrestore(&edmac->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_tx_status - check if a transaction is completed
|
|
* @chan: channel
|
|
* @cookie: transaction specific cookie
|
|
* @state: state of the transaction is stored here if given
|
|
*
|
|
* This function can be used to query state of a given transaction.
|
|
*/
|
|
static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
struct dma_tx_state *state)
|
|
{
|
|
return dma_cookie_status(chan, cookie, state);
|
|
}
|
|
|
|
/**
|
|
* ep93xx_dma_issue_pending - push pending transactions to the hardware
|
|
* @chan: channel
|
|
*
|
|
* When this function is called, all pending transactions are pushed to the
|
|
* hardware and executed.
|
|
*/
|
|
static void ep93xx_dma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan));
|
|
}
|
|
|
|
static int __init ep93xx_dma_probe(struct platform_device *pdev)
|
|
{
|
|
struct ep93xx_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
|
struct ep93xx_dma_engine *edma;
|
|
struct dma_device *dma_dev;
|
|
size_t edma_size;
|
|
int ret, i;
|
|
|
|
edma_size = pdata->num_channels * sizeof(struct ep93xx_dma_chan);
|
|
edma = kzalloc(sizeof(*edma) + edma_size, GFP_KERNEL);
|
|
if (!edma)
|
|
return -ENOMEM;
|
|
|
|
dma_dev = &edma->dma_dev;
|
|
edma->m2m = platform_get_device_id(pdev)->driver_data;
|
|
edma->num_channels = pdata->num_channels;
|
|
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
for (i = 0; i < pdata->num_channels; i++) {
|
|
const struct ep93xx_dma_chan_data *cdata = &pdata->channels[i];
|
|
struct ep93xx_dma_chan *edmac = &edma->channels[i];
|
|
|
|
edmac->chan.device = dma_dev;
|
|
edmac->regs = cdata->base;
|
|
edmac->irq = cdata->irq;
|
|
edmac->edma = edma;
|
|
|
|
edmac->clk = clk_get(NULL, cdata->name);
|
|
if (IS_ERR(edmac->clk)) {
|
|
dev_warn(&pdev->dev, "failed to get clock for %s\n",
|
|
cdata->name);
|
|
continue;
|
|
}
|
|
|
|
spin_lock_init(&edmac->lock);
|
|
INIT_LIST_HEAD(&edmac->active);
|
|
INIT_LIST_HEAD(&edmac->queue);
|
|
INIT_LIST_HEAD(&edmac->free_list);
|
|
tasklet_init(&edmac->tasklet, ep93xx_dma_tasklet,
|
|
(unsigned long)edmac);
|
|
|
|
list_add_tail(&edmac->chan.device_node,
|
|
&dma_dev->channels);
|
|
}
|
|
|
|
dma_cap_zero(dma_dev->cap_mask);
|
|
dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
|
|
|
|
dma_dev->dev = &pdev->dev;
|
|
dma_dev->device_alloc_chan_resources = ep93xx_dma_alloc_chan_resources;
|
|
dma_dev->device_free_chan_resources = ep93xx_dma_free_chan_resources;
|
|
dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;
|
|
dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;
|
|
dma_dev->device_config = ep93xx_dma_slave_config;
|
|
dma_dev->device_synchronize = ep93xx_dma_synchronize;
|
|
dma_dev->device_terminate_all = ep93xx_dma_terminate_all;
|
|
dma_dev->device_issue_pending = ep93xx_dma_issue_pending;
|
|
dma_dev->device_tx_status = ep93xx_dma_tx_status;
|
|
|
|
dma_set_max_seg_size(dma_dev->dev, DMA_MAX_CHAN_BYTES);
|
|
|
|
if (edma->m2m) {
|
|
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
dma_dev->device_prep_dma_memcpy = ep93xx_dma_prep_dma_memcpy;
|
|
|
|
edma->hw_setup = m2m_hw_setup;
|
|
edma->hw_shutdown = m2m_hw_shutdown;
|
|
edma->hw_submit = m2m_hw_submit;
|
|
edma->hw_interrupt = m2m_hw_interrupt;
|
|
} else {
|
|
dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
|
|
|
|
edma->hw_synchronize = m2p_hw_synchronize;
|
|
edma->hw_setup = m2p_hw_setup;
|
|
edma->hw_shutdown = m2p_hw_shutdown;
|
|
edma->hw_submit = m2p_hw_submit;
|
|
edma->hw_interrupt = m2p_hw_interrupt;
|
|
}
|
|
|
|
ret = dma_async_device_register(dma_dev);
|
|
if (unlikely(ret)) {
|
|
for (i = 0; i < edma->num_channels; i++) {
|
|
struct ep93xx_dma_chan *edmac = &edma->channels[i];
|
|
if (!IS_ERR_OR_NULL(edmac->clk))
|
|
clk_put(edmac->clk);
|
|
}
|
|
kfree(edma);
|
|
} else {
|
|
dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n",
|
|
edma->m2m ? "M" : "P");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct platform_device_id ep93xx_dma_driver_ids[] = {
|
|
{ "ep93xx-dma-m2p", 0 },
|
|
{ "ep93xx-dma-m2m", 1 },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver ep93xx_dma_driver = {
|
|
.driver = {
|
|
.name = "ep93xx-dma",
|
|
},
|
|
.id_table = ep93xx_dma_driver_ids,
|
|
};
|
|
|
|
static int __init ep93xx_dma_module_init(void)
|
|
{
|
|
return platform_driver_probe(&ep93xx_dma_driver, ep93xx_dma_probe);
|
|
}
|
|
subsys_initcall(ep93xx_dma_module_init);
|
|
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
|
|
MODULE_DESCRIPTION("EP93xx DMA driver");
|
|
MODULE_LICENSE("GPL");
|