2b79c56fb4
Some SGPIO PICs don't follow the standard very well and expect a certain number of clock cycles or port frames in each SGPIO pattern. Add two optional parameters in the DTB that can provide the number of extra clock cycles to be sent before and after SGPIO pattern. Read those parameters from the DTB and send the extra clock cycles. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Tejun Heo <tj@kernel.org>
45 lines
1.7 KiB
Plaintext
45 lines
1.7 KiB
Plaintext
* Calxeda AHCI SATA Controller
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SATA nodes are defined to describe on-chip Serial ATA controllers.
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The Calxeda SATA controller mostly conforms to the AHCI interface
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with some special extensions to add functionality.
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Each SATA controller should have its own node.
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Required properties:
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- compatible : compatible list, contains "calxeda,hb-ahci"
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- interrupts : <interrupt mapping for SATA IRQ>
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- reg : <registers mapping>
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Optional properties:
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- dma-coherent : Present if dma operations are coherent
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- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
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SATA port to a combophy and a lane within that
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combophy
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- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
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which indicates that the driver supports SGPIO
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indicator lights using the indicated GPIOs
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- calxeda,led-order : a u32 array that map port numbers to offsets within the
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SGPIO bitstream.
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- calxeda,tx-atten : a u32 array that contains TX attenuation override
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codes, one per port. The upper 3 bytes are always
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0 and thus ignored.
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- calxeda,pre-clocks : a u32 that indicates the number of additional clock
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cycles to transmit before sending an SGPIO pattern
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- calxeda,post-clocks: a u32 that indicates the number of additional clock
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cycles to transmit after sending an SGPIO pattern
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Example:
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sata@ffe08000 {
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compatible = "calxeda,hb-ahci";
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reg = <0xffe08000 0x1000>;
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interrupts = <115>;
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dma-coherent;
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calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
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&combophy0 2 &combophy0 3>;
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calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
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calxeda,led-order = <4 0 1 2 3>;
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calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
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calxeda,pre-clocks = <10>;
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calxeda,post-clocks = <0>;
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};
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