![Maxime Ripard](/assets/img/avatar_default.png)
On the Cortex-A9-based Armada SoCs, the MPIC is not the primary interrupt controller. Yet, it still has to handle some per-cpu interrupt. To do so, it is chained with the GIC using a per-cpu interrupt. However, the current code only call irq_set_chained_handler, which is called and enable that interrupt only on the boot CPU, which means that the parent per-CPU interrupt is never unmasked on the secondary CPUs, preventing the per-CPU interrupt to actually work as expected. This was not seen until now since the only MPIC PPI users were the Marvell timers that were not working, but not used either since the system use the ARM TWD by default, and the ethernet controllers, that are faking there interrupts as SPI, and don't really expect to have interrupts on the secondary cores anyway. Add a CPU notifier that will enable the PPI on the secondary cores when they are brought up. Cc: <stable@vger.kernel.org> # 3.15+ Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1425378443-28822-1-git-send-email-maxime.ripard@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
619 lines
16 KiB
C
619 lines
16 KiB
C
/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/cpu.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/irqdomain.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/msi.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
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#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
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#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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#define ARMADA_375_PPI_CAUSE (0x10)
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#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
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#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
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#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
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#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
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#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
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#define IPI_DOORBELL_START (0)
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#define IPI_DOORBELL_END (8)
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#define IPI_DOORBELL_MASK 0xFF
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#define PCI_MSI_DOORBELL_START (16)
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#define PCI_MSI_DOORBELL_NR (16)
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#define PCI_MSI_DOORBELL_END (32)
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#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static u32 doorbell_mask_reg;
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static int parent_irq;
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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static DEFINE_MUTEX(msi_used_lock);
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static phys_addr_t msi_doorbell_addr;
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#endif
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/*
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* In SMP mode:
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* For shared global interrupts, mask/unmask global enable bit
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* For CPU interrupts, mask/unmask the calling CPU's bit
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*/
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_SET_MASK_OFFS);
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hwirq, main_int_base +
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ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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else
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writel(hwirq, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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#ifdef CONFIG_PCI_MSI
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static int armada_370_xp_alloc_msi(void)
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{
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int hwirq;
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mutex_lock(&msi_used_lock);
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hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
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if (hwirq >= PCI_MSI_DOORBELL_NR)
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hwirq = -ENOSPC;
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else
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set_bit(hwirq, msi_used);
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mutex_unlock(&msi_used_lock);
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return hwirq;
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}
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static void armada_370_xp_free_msi(int hwirq)
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{
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mutex_lock(&msi_used_lock);
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if (!test_bit(hwirq, msi_used))
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pr_err("trying to free unused MSI#%d\n", hwirq);
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else
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clear_bit(hwirq, msi_used);
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mutex_unlock(&msi_used_lock);
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}
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static int armada_370_xp_setup_msi_irq(struct msi_controller *chip,
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struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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struct msi_msg msg;
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int virq, hwirq;
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/* We support MSI, but not MSI-X */
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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hwirq = armada_370_xp_alloc_msi();
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if (hwirq < 0)
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return hwirq;
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virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
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if (!virq) {
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armada_370_xp_free_msi(hwirq);
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return -EINVAL;
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}
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irq_set_msi_desc(virq, desc);
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msg.address_lo = msi_doorbell_addr;
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msg.address_hi = 0;
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msg.data = 0xf00 | (hwirq + 16);
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pci_write_msi_msg(virq, &msg);
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return 0;
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}
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static void armada_370_xp_teardown_msi_irq(struct msi_controller *chip,
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unsigned int irq)
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{
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struct irq_data *d = irq_get_irq_data(irq);
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unsigned long hwirq = d->hwirq;
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irq_dispose_mapping(irq);
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armada_370_xp_free_msi(hwirq);
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}
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static struct irq_chip armada_370_xp_msi_irq_chip = {
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.name = "armada_370_xp_msi_irq",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
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handle_simple_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
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.map = armada_370_xp_msi_map,
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};
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static int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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struct msi_controller *msi_chip;
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u32 reg;
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int ret;
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msi_doorbell_addr = main_int_phys_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS;
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msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
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if (!msi_chip)
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return -ENOMEM;
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msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
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msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
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msi_chip->of_node = node;
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armada_370_xp_msi_domain =
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irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
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&armada_370_xp_msi_irq_ops,
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NULL);
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if (!armada_370_xp_msi_domain) {
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kfree(msi_chip);
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return -ENOMEM;
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}
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ret = of_pci_msi_chip_add(msi_chip);
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if (ret < 0) {
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irq_domain_remove(armada_370_xp_msi_domain);
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kfree(msi_chip);
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return ret;
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}
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reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
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| PCI_MSI_DOORBELL_MASK;
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writel(reg, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask IPI interrupt */
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writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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return 0;
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}
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#else
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static inline int armada_370_xp_msi_init(struct device_node *node,
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phys_addr_t main_int_phys_base)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_SMP
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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static int armada_xp_set_affinity(struct irq_data *d,
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const struct cpumask *mask_val, bool force)
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{
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long reg, mask;
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int cpu;
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/* Select a single core from the affinity mask which is online */
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cpu = cpumask_any_and(mask_val, cpu_online_mask);
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mask = 1UL << cpu_logical_map(cpu);
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raw_spin_lock(&irq_controller_lock);
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reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
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reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
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writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
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raw_spin_unlock(&irq_controller_lock);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip armada_370_xp_irq_chip = {
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.name = "armada_370_xp_irq",
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.irq_mask = armada_370_xp_irq_mask,
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.irq_mask_ack = armada_370_xp_irq_mask,
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.irq_unmask = armada_370_xp_irq_unmask,
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#ifdef CONFIG_SMP
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.irq_set_affinity = armada_xp_set_affinity,
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#endif
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};
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static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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armada_370_xp_irq_mask(irq_get_irq_data(virq));
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if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
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writel(hw, per_cpu_int_base +
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ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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else
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_status_flags(virq, IRQ_LEVEL);
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if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
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irq_set_percpu_devid(virq);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_percpu_devid_irq);
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} else {
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_level_irq);
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}
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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#ifdef CONFIG_SMP
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static void armada_mpic_send_doorbell(const struct cpumask *mask,
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unsigned int irq)
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{
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int cpu;
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unsigned long map = 0;
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/* Convert our logical CPU mask into a physical one. */
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for_each_cpu(cpu, mask)
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map |= 1 << cpu_logical_map(cpu);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* submit softirq */
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writel((map << 8) | irq, main_int_base +
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ARMADA_370_XP_SW_TRIG_INT_OFFS);
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}
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static void armada_xp_mpic_smp_cpu_init(void)
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{
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u32 control;
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int nr_irqs, i;
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control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
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nr_irqs = (control >> 2) & 0x3ff;
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for (i = 0; i < nr_irqs; i++)
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writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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/* Clear pending IPIs */
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writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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/* Enable first 8 IPIs */
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writel(IPI_DOORBELL_MASK, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
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/* Unmask IPI interrupt */
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writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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armada_xp_mpic_smp_cpu_init();
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return NOTIFY_OK;
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}
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static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
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.notifier_call = armada_xp_mpic_secondary_init,
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.priority = 100,
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};
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static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
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return NOTIFY_OK;
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}
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static struct notifier_block mpic_cascaded_cpu_notifier = {
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.notifier_call = mpic_cascaded_secondary_init,
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.priority = 100,
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};
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#endif /* CONFIG_SMP */
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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.map = armada_370_xp_mpic_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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#ifdef CONFIG_PCI_MSI
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static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
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{
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u32 msimask, msinr;
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msimask = readl_relaxed(per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
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& PCI_MSI_DOORBELL_MASK;
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writel(~msimask, per_cpu_int_base +
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ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
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for (msinr = PCI_MSI_DOORBELL_START;
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msinr < PCI_MSI_DOORBELL_END; msinr++) {
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int irq;
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if (!(msimask & BIT(msinr)))
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continue;
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if (is_chained) {
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irq = irq_find_mapping(armada_370_xp_msi_domain,
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msinr - 16);
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generic_handle_irq(irq);
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} else {
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irq = msinr - 16;
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handle_domain_irq(armada_370_xp_msi_domain,
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irq, regs);
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}
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}
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}
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#else
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static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
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#endif
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static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
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struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned long irqmap, irqn, irqsrc, cpuid;
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unsigned int cascade_irq;
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chained_irq_enter(chip, desc);
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irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
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cpuid = cpu_logical_map(smp_processor_id());
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for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
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irqsrc = readl_relaxed(main_int_base +
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ARMADA_370_XP_INT_SOURCE_CTL(irqn));
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/* Check if the interrupt is not masked on current CPU.
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* Test IRQ (0-1) and FIQ (8-9) mask bits.
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*/
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if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
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continue;
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if (irqn == 1) {
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armada_370_xp_handle_msi_irq(NULL, true);
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continue;
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}
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|
|
cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
|
|
generic_handle_irq(cascade_irq);
|
|
}
|
|
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
|
|
static void __exception_irq_entry
|
|
armada_370_xp_handle_irq(struct pt_regs *regs)
|
|
{
|
|
u32 irqstat, irqnr;
|
|
|
|
do {
|
|
irqstat = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_CPU_INTACK_OFFS);
|
|
irqnr = irqstat & 0x3FF;
|
|
|
|
if (irqnr > 1022)
|
|
break;
|
|
|
|
if (irqnr > 1) {
|
|
handle_domain_irq(armada_370_xp_mpic_domain,
|
|
irqnr, regs);
|
|
continue;
|
|
}
|
|
|
|
/* MSI handling */
|
|
if (irqnr == 1)
|
|
armada_370_xp_handle_msi_irq(regs, false);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* IPI Handling */
|
|
if (irqnr == 0) {
|
|
u32 ipimask, ipinr;
|
|
|
|
ipimask = readl_relaxed(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
|
|
& IPI_DOORBELL_MASK;
|
|
|
|
writel(~ipimask, per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
|
|
|
|
/* Handle all pending doorbells */
|
|
for (ipinr = IPI_DOORBELL_START;
|
|
ipinr < IPI_DOORBELL_END; ipinr++) {
|
|
if (ipimask & (0x1 << ipinr))
|
|
handle_IPI(ipinr, regs);
|
|
}
|
|
continue;
|
|
}
|
|
#endif
|
|
|
|
} while (1);
|
|
}
|
|
|
|
static int armada_370_xp_mpic_suspend(void)
|
|
{
|
|
doorbell_mask_reg = readl(per_cpu_int_base +
|
|
ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
return 0;
|
|
}
|
|
|
|
static void armada_370_xp_mpic_resume(void)
|
|
{
|
|
int nirqs;
|
|
irq_hw_number_t irq;
|
|
|
|
/* Re-enable interrupts */
|
|
nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
|
|
for (irq = 0; irq < nirqs; irq++) {
|
|
struct irq_data *data;
|
|
int virq;
|
|
|
|
virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
|
|
if (virq == 0)
|
|
continue;
|
|
|
|
if (irq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
|
writel(irq, per_cpu_int_base +
|
|
ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
else
|
|
writel(irq, main_int_base +
|
|
ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
|
|
|
data = irq_get_irq_data(virq);
|
|
if (!irqd_irq_disabled(data))
|
|
armada_370_xp_irq_unmask(data);
|
|
}
|
|
|
|
/* Reconfigure doorbells for IPIs and MSIs */
|
|
writel(doorbell_mask_reg,
|
|
per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
|
|
if (doorbell_mask_reg & IPI_DOORBELL_MASK)
|
|
writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
|
|
writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
|
|
}
|
|
|
|
struct syscore_ops armada_370_xp_mpic_syscore_ops = {
|
|
.suspend = armada_370_xp_mpic_suspend,
|
|
.resume = armada_370_xp_mpic_resume,
|
|
};
|
|
|
|
static int __init armada_370_xp_mpic_of_init(struct device_node *node,
|
|
struct device_node *parent)
|
|
{
|
|
struct resource main_int_res, per_cpu_int_res;
|
|
int nr_irqs, i;
|
|
u32 control;
|
|
|
|
BUG_ON(of_address_to_resource(node, 0, &main_int_res));
|
|
BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
|
|
|
|
BUG_ON(!request_mem_region(main_int_res.start,
|
|
resource_size(&main_int_res),
|
|
node->full_name));
|
|
BUG_ON(!request_mem_region(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res),
|
|
node->full_name));
|
|
|
|
main_int_base = ioremap(main_int_res.start,
|
|
resource_size(&main_int_res));
|
|
BUG_ON(!main_int_base);
|
|
|
|
per_cpu_int_base = ioremap(per_cpu_int_res.start,
|
|
resource_size(&per_cpu_int_res));
|
|
BUG_ON(!per_cpu_int_base);
|
|
|
|
control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
|
|
nr_irqs = (control >> 2) & 0x3ff;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
|
|
|
|
armada_370_xp_mpic_domain =
|
|
irq_domain_add_linear(node, nr_irqs,
|
|
&armada_370_xp_mpic_irq_ops, NULL);
|
|
|
|
BUG_ON(!armada_370_xp_mpic_domain);
|
|
|
|
#ifdef CONFIG_SMP
|
|
armada_xp_mpic_smp_cpu_init();
|
|
#endif
|
|
|
|
armada_370_xp_msi_init(node, main_int_res.start);
|
|
|
|
parent_irq = irq_of_parse_and_map(node, 0);
|
|
if (parent_irq <= 0) {
|
|
irq_set_default_host(armada_370_xp_mpic_domain);
|
|
set_handle_irq(armada_370_xp_handle_irq);
|
|
#ifdef CONFIG_SMP
|
|
set_smp_cross_call(armada_mpic_send_doorbell);
|
|
register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
|
|
#endif
|
|
} else {
|
|
#ifdef CONFIG_SMP
|
|
register_cpu_notifier(&mpic_cascaded_cpu_notifier);
|
|
#endif
|
|
irq_set_chained_handler(parent_irq,
|
|
armada_370_xp_mpic_handle_cascade_irq);
|
|
}
|
|
|
|
register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
|