![Andy Shevchenko](/assets/img/avatar_default.png)
The commitd297933cc7
(spi: dw: Fix detecting FIFO depth) tries to fix the logic of the FIFO detection based on the description on the comments. However, there is a slight difference between numbers in TX Level and TX FIFO size. So, by specification the FIFO size would be in a range 2-256 bytes. From TX Level prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes. Hence there are currently two issues: a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be either 0 or 1 byte; b) FIFO size is incorrectly decreased by 1 which already done by meaning of TX Level register. This patch fixes it eventually right. Fixes:d297933cc7
(spi: dw: Fix detecting FIFO depth) Reviewed-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
746 lines
18 KiB
C
746 lines
18 KiB
C
/*
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* Designware SPI core controller driver (refer pxa2xx_spi.c)
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*
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* Copyright (c) 2009, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/highmem.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include "spi-dw.h"
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#endif
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#define START_STATE ((void *)0)
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#define RUNNING_STATE ((void *)1)
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#define DONE_STATE ((void *)2)
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#define ERROR_STATE ((void *)-1)
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/* Slave spi_dev related */
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struct chip_data {
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u16 cr0;
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u8 cs; /* chip select pin */
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u8 n_bytes; /* current is a 1/2/4 byte op */
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u8 tmode; /* TR/TO/RO/EEPROM */
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u8 type; /* SPI/SSP/MicroWire */
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u8 poll_mode; /* 1 means use poll mode */
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u32 dma_width;
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u32 rx_threshold;
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u32 tx_threshold;
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u8 enable_dma;
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u8 bits_per_word;
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u16 clk_div; /* baud rate divider */
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u32 speed_hz; /* baud rate */
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_DEBUG_FS
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#define SPI_REGS_BUFSIZE 1024
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static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct dw_spi *dws = file->private_data;
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char *buf;
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u32 len = 0;
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ssize_t ret;
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buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
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if (!buf)
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return 0;
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"%s registers:\n", dev_name(&dws->master->dev));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
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len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
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"=================================\n");
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
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kfree(buf);
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return ret;
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}
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static const struct file_operations dw_spi_regs_ops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.read = dw_spi_show_regs,
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.llseek = default_llseek,
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};
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static int dw_spi_debugfs_init(struct dw_spi *dws)
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{
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dws->debugfs = debugfs_create_dir("dw_spi", NULL);
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if (!dws->debugfs)
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return -ENOMEM;
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debugfs_create_file("registers", S_IFREG | S_IRUGO,
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dws->debugfs, (void *)dws, &dw_spi_regs_ops);
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return 0;
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}
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static void dw_spi_debugfs_remove(struct dw_spi *dws)
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{
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debugfs_remove_recursive(dws->debugfs);
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}
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#else
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static inline int dw_spi_debugfs_init(struct dw_spi *dws)
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{
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return 0;
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}
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static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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/* Return the max entries we can fill into tx fifo */
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static inline u32 tx_max(struct dw_spi *dws)
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{
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u32 tx_left, tx_room, rxtx_gap;
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tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
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tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
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/*
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* Another concern is about the tx/rx mismatch, we
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* though to use (dws->fifo_len - rxflr - txflr) as
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* one maximum value for tx, but it doesn't cover the
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* data which is out of tx/rx fifo and inside the
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* shift registers. So a control from sw point of
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* view is taken.
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*/
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rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
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/ dws->n_bytes;
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return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
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}
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/* Return the max entries we should read out of rx fifo */
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static inline u32 rx_max(struct dw_spi *dws)
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{
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u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
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return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
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}
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static void dw_writer(struct dw_spi *dws)
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{
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u32 max = tx_max(dws);
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u16 txw = 0;
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while (max--) {
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/* Set the tx word if the transfer's original "tx" is not null */
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if (dws->tx_end - dws->len) {
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if (dws->n_bytes == 1)
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txw = *(u8 *)(dws->tx);
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else
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txw = *(u16 *)(dws->tx);
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}
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dw_writew(dws, DW_SPI_DR, txw);
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dws->tx += dws->n_bytes;
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}
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}
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static void dw_reader(struct dw_spi *dws)
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{
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u32 max = rx_max(dws);
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u16 rxw;
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while (max--) {
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rxw = dw_readw(dws, DW_SPI_DR);
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/* Care rx only if the transfer's original "rx" is not null */
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if (dws->rx_end - dws->len) {
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if (dws->n_bytes == 1)
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*(u8 *)(dws->rx) = rxw;
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else
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*(u16 *)(dws->rx) = rxw;
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}
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dws->rx += dws->n_bytes;
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}
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}
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static void *next_transfer(struct dw_spi *dws)
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{
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struct spi_message *msg = dws->cur_msg;
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struct spi_transfer *trans = dws->cur_transfer;
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/* Move to next transfer */
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if (trans->transfer_list.next != &msg->transfers) {
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dws->cur_transfer =
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list_entry(trans->transfer_list.next,
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struct spi_transfer,
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transfer_list);
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return RUNNING_STATE;
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}
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return DONE_STATE;
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}
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/*
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* Note: first step is the protocol driver prepares
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* a dma-capable memory, and this func just need translate
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* the virt addr to physical
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*/
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static int map_dma_buffers(struct dw_spi *dws)
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{
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if (!dws->cur_msg->is_dma_mapped
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|| !dws->dma_inited
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|| !dws->cur_chip->enable_dma
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|| !dws->dma_ops)
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return 0;
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if (dws->cur_transfer->tx_dma)
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dws->tx_dma = dws->cur_transfer->tx_dma;
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if (dws->cur_transfer->rx_dma)
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dws->rx_dma = dws->cur_transfer->rx_dma;
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return 1;
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}
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/* Caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct dw_spi *dws)
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{
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struct spi_transfer *last_transfer;
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struct spi_message *msg;
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msg = dws->cur_msg;
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dws->cur_msg = NULL;
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dws->cur_transfer = NULL;
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dws->prev_chip = dws->cur_chip;
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dws->cur_chip = NULL;
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dws->dma_mapped = 0;
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last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
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transfer_list);
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if (!last_transfer->cs_change)
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spi_chip_sel(dws, msg->spi, 0);
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spi_finalize_current_message(dws->master);
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}
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static void int_error_stop(struct dw_spi *dws, const char *msg)
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{
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/* Stop the hw */
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spi_enable_chip(dws, 0);
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dev_err(&dws->master->dev, "%s\n", msg);
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dws->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&dws->pump_transfers);
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}
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void dw_spi_xfer_done(struct dw_spi *dws)
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{
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/* Update total byte transferred return count actual bytes read */
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dws->cur_msg->actual_length += dws->len;
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/* Move to next transfer */
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dws->cur_msg->state = next_transfer(dws);
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/* Handle end of message */
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if (dws->cur_msg->state == DONE_STATE) {
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dws->cur_msg->status = 0;
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giveback(dws);
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} else
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tasklet_schedule(&dws->pump_transfers);
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}
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EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
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static irqreturn_t interrupt_transfer(struct dw_spi *dws)
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{
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u16 irq_status = dw_readw(dws, DW_SPI_ISR);
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/* Error handling */
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if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
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dw_readw(dws, DW_SPI_TXOICR);
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dw_readw(dws, DW_SPI_RXOICR);
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dw_readw(dws, DW_SPI_RXUICR);
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int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
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return IRQ_HANDLED;
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}
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dw_reader(dws);
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if (dws->rx_end == dws->rx) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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dw_spi_xfer_done(dws);
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return IRQ_HANDLED;
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}
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if (irq_status & SPI_INT_TXEI) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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dw_writer(dws);
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/* Enable TX irq always, it will be disabled when RX finished */
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spi_umask_intr(dws, SPI_INT_TXEI);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t dw_spi_irq(int irq, void *dev_id)
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{
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struct dw_spi *dws = dev_id;
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u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
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if (!irq_status)
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return IRQ_NONE;
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if (!dws->cur_msg) {
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spi_mask_intr(dws, SPI_INT_TXEI);
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return IRQ_HANDLED;
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}
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return dws->transfer_handler(dws);
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}
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/* Must be called inside pump_transfers() */
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static void poll_transfer(struct dw_spi *dws)
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{
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do {
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dw_writer(dws);
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dw_reader(dws);
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cpu_relax();
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} while (dws->rx_end > dws->rx);
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dw_spi_xfer_done(dws);
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}
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static void pump_transfers(unsigned long data)
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{
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struct dw_spi *dws = (struct dw_spi *)data;
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struct spi_message *message = NULL;
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct spi_device *spi = NULL;
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struct chip_data *chip = NULL;
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u8 bits = 0;
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u8 imask = 0;
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u8 cs_change = 0;
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u16 txint_level = 0;
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u16 clk_div = 0;
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u32 speed = 0;
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u32 cr0 = 0;
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/* Get current state information */
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message = dws->cur_msg;
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transfer = dws->cur_transfer;
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chip = dws->cur_chip;
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spi = message->spi;
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if (message->state == ERROR_STATE) {
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message->status = -EIO;
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goto early_exit;
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}
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/* Handle end of message */
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if (message->state == DONE_STATE) {
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message->status = 0;
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goto early_exit;
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}
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/* Delay if requested at end of transfer */
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if (message->state == RUNNING_STATE) {
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previous = list_entry(transfer->transfer_list.prev,
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struct spi_transfer,
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transfer_list);
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if (previous->delay_usecs)
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udelay(previous->delay_usecs);
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}
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dws->n_bytes = chip->n_bytes;
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dws->dma_width = chip->dma_width;
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dws->cs_control = chip->cs_control;
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dws->rx_dma = transfer->rx_dma;
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dws->tx_dma = transfer->tx_dma;
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dws->tx = (void *)transfer->tx_buf;
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dws->tx_end = dws->tx + transfer->len;
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dws->rx = transfer->rx_buf;
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dws->rx_end = dws->rx + transfer->len;
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dws->len = dws->cur_transfer->len;
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if (chip != dws->prev_chip)
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cs_change = 1;
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cr0 = chip->cr0;
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/* Handle per transfer options for bpw and speed */
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if (transfer->speed_hz) {
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speed = chip->speed_hz;
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if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
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speed = transfer->speed_hz;
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/* clk_div doesn't support odd number */
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clk_div = dws->max_freq / speed;
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clk_div = (clk_div + 1) & 0xfffe;
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chip->speed_hz = speed;
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chip->clk_div = clk_div;
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}
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}
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if (transfer->bits_per_word) {
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bits = transfer->bits_per_word;
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dws->n_bytes = dws->dma_width = bits >> 3;
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cr0 = (bits - 1)
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| (chip->type << SPI_FRF_OFFSET)
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| (spi->mode << SPI_MODE_OFFSET)
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| (chip->tmode << SPI_TMOD_OFFSET);
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}
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message->state = RUNNING_STATE;
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/*
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* Adjust transfer mode if necessary. Requires platform dependent
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* chipselect mechanism.
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*/
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if (dws->cs_control) {
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if (dws->rx && dws->tx)
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chip->tmode = SPI_TMOD_TR;
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else if (dws->rx)
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chip->tmode = SPI_TMOD_RO;
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else
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chip->tmode = SPI_TMOD_TO;
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cr0 &= ~SPI_TMOD_MASK;
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cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
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}
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/* Check if current transfer is a DMA transaction */
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dws->dma_mapped = map_dma_buffers(dws);
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/*
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* Interrupt mode
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* we only need set the TXEI IRQ, as TX/RX always happen syncronizely
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*/
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if (!dws->dma_mapped && !chip->poll_mode) {
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int templen = dws->len / dws->n_bytes;
|
|
|
|
txint_level = dws->fifo_len / 2;
|
|
txint_level = (templen > txint_level) ? txint_level : templen;
|
|
|
|
imask |= SPI_INT_TXEI | SPI_INT_TXOI |
|
|
SPI_INT_RXUI | SPI_INT_RXOI;
|
|
dws->transfer_handler = interrupt_transfer;
|
|
}
|
|
|
|
/*
|
|
* Reprogram registers only if
|
|
* 1. chip select changes
|
|
* 2. clk_div is changed
|
|
* 3. control value changes
|
|
*/
|
|
if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
|
|
spi_enable_chip(dws, 0);
|
|
|
|
if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
|
|
dw_writew(dws, DW_SPI_CTRL0, cr0);
|
|
|
|
spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
|
|
spi_chip_sel(dws, spi, 1);
|
|
|
|
/* Set the interrupt mask, for poll mode just disable all int */
|
|
spi_mask_intr(dws, 0xff);
|
|
if (imask)
|
|
spi_umask_intr(dws, imask);
|
|
if (txint_level)
|
|
dw_writew(dws, DW_SPI_TXFLTR, txint_level);
|
|
|
|
spi_enable_chip(dws, 1);
|
|
if (cs_change)
|
|
dws->prev_chip = chip;
|
|
}
|
|
|
|
if (dws->dma_mapped)
|
|
dws->dma_ops->dma_transfer(dws, cs_change);
|
|
|
|
if (chip->poll_mode)
|
|
poll_transfer(dws);
|
|
|
|
return;
|
|
|
|
early_exit:
|
|
giveback(dws);
|
|
}
|
|
|
|
static int dw_spi_transfer_one_message(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct dw_spi *dws = spi_master_get_devdata(master);
|
|
|
|
dws->cur_msg = msg;
|
|
/* Initial message state */
|
|
dws->cur_msg->state = START_STATE;
|
|
dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
|
|
struct spi_transfer,
|
|
transfer_list);
|
|
dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
|
|
|
|
/* Launch transfers */
|
|
tasklet_schedule(&dws->pump_transfers);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This may be called twice for each spi dev */
|
|
static int dw_spi_setup(struct spi_device *spi)
|
|
{
|
|
struct dw_spi_chip *chip_info = NULL;
|
|
struct chip_data *chip;
|
|
int ret;
|
|
|
|
/* Only alloc on first setup */
|
|
chip = spi_get_ctldata(spi);
|
|
if (!chip) {
|
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
|
if (!chip)
|
|
return -ENOMEM;
|
|
spi_set_ctldata(spi, chip);
|
|
}
|
|
|
|
/*
|
|
* Protocol drivers may change the chip settings, so...
|
|
* if chip_info exists, use it
|
|
*/
|
|
chip_info = spi->controller_data;
|
|
|
|
/* chip_info doesn't always exist */
|
|
if (chip_info) {
|
|
if (chip_info->cs_control)
|
|
chip->cs_control = chip_info->cs_control;
|
|
|
|
chip->poll_mode = chip_info->poll_mode;
|
|
chip->type = chip_info->type;
|
|
|
|
chip->rx_threshold = 0;
|
|
chip->tx_threshold = 0;
|
|
|
|
chip->enable_dma = chip_info->enable_dma;
|
|
}
|
|
|
|
if (spi->bits_per_word == 8) {
|
|
chip->n_bytes = 1;
|
|
chip->dma_width = 1;
|
|
} else if (spi->bits_per_word == 16) {
|
|
chip->n_bytes = 2;
|
|
chip->dma_width = 2;
|
|
}
|
|
chip->bits_per_word = spi->bits_per_word;
|
|
|
|
if (!spi->max_speed_hz) {
|
|
dev_err(&spi->dev, "No max speed HZ parameter\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->tmode = 0; /* Tx & Rx */
|
|
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
|
|
chip->cr0 = (chip->bits_per_word - 1)
|
|
| (chip->type << SPI_FRF_OFFSET)
|
|
| (spi->mode << SPI_MODE_OFFSET)
|
|
| (chip->tmode << SPI_TMOD_OFFSET);
|
|
|
|
if (spi->mode & SPI_LOOP)
|
|
chip->cr0 |= 1 << SPI_SRL_OFFSET;
|
|
|
|
if (gpio_is_valid(spi->cs_gpio)) {
|
|
ret = gpio_direction_output(spi->cs_gpio,
|
|
!(spi->mode & SPI_CS_HIGH));
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dw_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
struct chip_data *chip = spi_get_ctldata(spi);
|
|
|
|
kfree(chip);
|
|
spi_set_ctldata(spi, NULL);
|
|
}
|
|
|
|
/* Restart the controller, disable all interrupts, clean rx fifo */
|
|
static void spi_hw_init(struct device *dev, struct dw_spi *dws)
|
|
{
|
|
spi_enable_chip(dws, 0);
|
|
spi_mask_intr(dws, 0xff);
|
|
spi_enable_chip(dws, 1);
|
|
|
|
/*
|
|
* Try to detect the FIFO depth if not set by interface driver,
|
|
* the depth could be from 2 to 256 from HW spec
|
|
*/
|
|
if (!dws->fifo_len) {
|
|
u32 fifo;
|
|
|
|
for (fifo = 1; fifo < 256; fifo++) {
|
|
dw_writew(dws, DW_SPI_TXFLTR, fifo);
|
|
if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
|
|
break;
|
|
}
|
|
dw_writew(dws, DW_SPI_TXFLTR, 0);
|
|
|
|
dws->fifo_len = (fifo == 1) ? 0 : fifo;
|
|
dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
|
|
}
|
|
}
|
|
|
|
int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
|
|
{
|
|
struct spi_master *master;
|
|
int ret;
|
|
|
|
BUG_ON(dws == NULL);
|
|
|
|
master = spi_alloc_master(dev, 0);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
dws->master = master;
|
|
dws->type = SSI_MOTO_SPI;
|
|
dws->prev_chip = NULL;
|
|
dws->dma_inited = 0;
|
|
dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
|
|
snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
|
|
|
|
ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
|
|
dws->name, dws);
|
|
if (ret < 0) {
|
|
dev_err(&master->dev, "can not get IRQ\n");
|
|
goto err_free_master;
|
|
}
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
|
|
master->bus_num = dws->bus_num;
|
|
master->num_chipselect = dws->num_cs;
|
|
master->setup = dw_spi_setup;
|
|
master->cleanup = dw_spi_cleanup;
|
|
master->transfer_one_message = dw_spi_transfer_one_message;
|
|
master->max_speed_hz = dws->max_freq;
|
|
master->dev.of_node = dev->of_node;
|
|
|
|
/* Basic HW init */
|
|
spi_hw_init(dev, dws);
|
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_init) {
|
|
ret = dws->dma_ops->dma_init(dws);
|
|
if (ret) {
|
|
dev_warn(dev, "DMA init failed\n");
|
|
dws->dma_inited = 0;
|
|
}
|
|
}
|
|
|
|
tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
|
|
|
|
spi_master_set_devdata(master, dws);
|
|
ret = devm_spi_register_master(dev, master);
|
|
if (ret) {
|
|
dev_err(&master->dev, "problem registering spi master\n");
|
|
goto err_dma_exit;
|
|
}
|
|
|
|
dw_spi_debugfs_init(dws);
|
|
return 0;
|
|
|
|
err_dma_exit:
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
dws->dma_ops->dma_exit(dws);
|
|
spi_enable_chip(dws, 0);
|
|
err_free_master:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_add_host);
|
|
|
|
void dw_spi_remove_host(struct dw_spi *dws)
|
|
{
|
|
if (!dws)
|
|
return;
|
|
dw_spi_debugfs_remove(dws);
|
|
|
|
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
|
dws->dma_ops->dma_exit(dws);
|
|
spi_enable_chip(dws, 0);
|
|
/* Disable clk */
|
|
spi_set_clk(dws, 0);
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_remove_host);
|
|
|
|
int dw_spi_suspend_host(struct dw_spi *dws)
|
|
{
|
|
int ret = 0;
|
|
|
|
ret = spi_master_suspend(dws->master);
|
|
if (ret)
|
|
return ret;
|
|
spi_enable_chip(dws, 0);
|
|
spi_set_clk(dws, 0);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
|
|
|
|
int dw_spi_resume_host(struct dw_spi *dws)
|
|
{
|
|
int ret;
|
|
|
|
spi_hw_init(&dws->master->dev, dws);
|
|
ret = spi_master_resume(dws->master);
|
|
if (ret)
|
|
dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(dw_spi_resume_host);
|
|
|
|
MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
|
|
MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
|
|
MODULE_LICENSE("GPL v2");
|