![Sifan Naeem](/assets/img/avatar_default.png)
Maximum transfer length supported by SPFI is 65535, this is limited by the number of bits available in SPFI TSize register to represent the transfer size. For transfer requests larger than the maximum supported the driver will return an invalid argument error. Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
743 lines
19 KiB
C
743 lines
19 KiB
C
/*
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* IMG SPFI controller driver
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*
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* Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/scatterlist.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spinlock.h>
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#define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
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#define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
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#define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
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#define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
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#define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
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#define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
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#define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
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#define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
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#define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
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#define SPFI_CONTROL 0x14
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#define SPFI_CONTROL_CONTINUE BIT(12)
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#define SPFI_CONTROL_SOFT_RESET BIT(11)
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#define SPFI_CONTROL_SEND_DMA BIT(10)
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#define SPFI_CONTROL_GET_DMA BIT(9)
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#define SPFI_CONTROL_TMODE_SHIFT 5
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#define SPFI_CONTROL_TMODE_MASK 0x7
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#define SPFI_CONTROL_TMODE_SINGLE 0
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#define SPFI_CONTROL_TMODE_DUAL 1
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#define SPFI_CONTROL_TMODE_QUAD 2
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#define SPFI_CONTROL_SPFI_EN BIT(0)
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#define SPFI_TRANSACTION 0x18
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#define SPFI_TRANSACTION_TSIZE_SHIFT 16
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#define SPFI_TRANSACTION_TSIZE_MASK 0xffff
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#define SPFI_PORT_STATE 0x1c
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#define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
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#define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
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#define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
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#define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
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#define SPFI_TX_32BIT_VALID_DATA 0x20
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#define SPFI_TX_8BIT_VALID_DATA 0x24
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#define SPFI_RX_32BIT_VALID_DATA 0x28
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#define SPFI_RX_8BIT_VALID_DATA 0x2c
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#define SPFI_INTERRUPT_STATUS 0x30
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#define SPFI_INTERRUPT_ENABLE 0x34
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#define SPFI_INTERRUPT_CLEAR 0x38
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#define SPFI_INTERRUPT_IACCESS BIT(12)
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#define SPFI_INTERRUPT_GDEX8BIT BIT(11)
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#define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
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#define SPFI_INTERRUPT_GDFUL BIT(8)
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#define SPFI_INTERRUPT_GDHF BIT(7)
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#define SPFI_INTERRUPT_GDEX32BIT BIT(6)
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#define SPFI_INTERRUPT_GDTRIG BIT(5)
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#define SPFI_INTERRUPT_SDFUL BIT(3)
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#define SPFI_INTERRUPT_SDHF BIT(2)
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#define SPFI_INTERRUPT_SDE BIT(1)
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#define SPFI_INTERRUPT_SDTRIG BIT(0)
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/*
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* There are four parallel FIFOs of 16 bytes each. The word buffer
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* (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
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* effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
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* accesses only a single FIFO, resulting in an effective FIFO size of
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* 16 bytes.
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*/
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#define SPFI_32BIT_FIFO_SIZE 64
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#define SPFI_8BIT_FIFO_SIZE 16
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struct img_spfi {
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struct device *dev;
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struct spi_master *master;
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spinlock_t lock;
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void __iomem *regs;
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phys_addr_t phys;
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int irq;
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struct clk *spfi_clk;
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struct clk *sys_clk;
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struct dma_chan *rx_ch;
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struct dma_chan *tx_ch;
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bool tx_dma_busy;
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bool rx_dma_busy;
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};
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static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
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{
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return readl(spfi->regs + reg);
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}
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static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
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{
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writel(val, spfi->regs + reg);
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}
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static inline void spfi_start(struct img_spfi *spfi)
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{
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u32 val;
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val = spfi_readl(spfi, SPFI_CONTROL);
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val |= SPFI_CONTROL_SPFI_EN;
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spfi_writel(spfi, val, SPFI_CONTROL);
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}
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static inline void spfi_stop(struct img_spfi *spfi)
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{
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u32 val;
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val = spfi_readl(spfi, SPFI_CONTROL);
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val &= ~SPFI_CONTROL_SPFI_EN;
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spfi_writel(spfi, val, SPFI_CONTROL);
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}
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static inline void spfi_reset(struct img_spfi *spfi)
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{
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spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
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udelay(1);
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spfi_writel(spfi, 0, SPFI_CONTROL);
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}
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static void spfi_flush_tx_fifo(struct img_spfi *spfi)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR);
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while (time_before(jiffies, timeout)) {
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if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &
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SPFI_INTERRUPT_SDE)
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return;
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cpu_relax();
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}
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dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n");
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spfi_reset(spfi);
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}
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static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
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unsigned int max)
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{
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unsigned int count = 0;
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u32 status;
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while (count < max / 4) {
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spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
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status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
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if (status & SPFI_INTERRUPT_SDFUL)
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break;
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spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
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count++;
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}
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return count * 4;
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}
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static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
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unsigned int max)
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{
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unsigned int count = 0;
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u32 status;
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while (count < max) {
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spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
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status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
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if (status & SPFI_INTERRUPT_SDFUL)
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break;
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spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
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count++;
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}
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return count;
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}
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static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
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unsigned int max)
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{
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unsigned int count = 0;
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u32 status;
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while (count < max / 4) {
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spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
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SPFI_INTERRUPT_CLEAR);
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status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
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if (!(status & SPFI_INTERRUPT_GDEX32BIT))
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break;
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buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
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count++;
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}
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return count * 4;
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}
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static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
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unsigned int max)
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{
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unsigned int count = 0;
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u32 status;
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while (count < max) {
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spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
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SPFI_INTERRUPT_CLEAR);
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status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
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if (!(status & SPFI_INTERRUPT_GDEX8BIT))
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break;
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buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
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count++;
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}
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return count;
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}
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static int img_spfi_start_pio(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct img_spfi *spfi = spi_master_get_devdata(spi->master);
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unsigned int tx_bytes = 0, rx_bytes = 0;
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const void *tx_buf = xfer->tx_buf;
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void *rx_buf = xfer->rx_buf;
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unsigned long timeout;
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if (tx_buf)
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tx_bytes = xfer->len;
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if (rx_buf)
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rx_bytes = xfer->len;
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spfi_start(spfi);
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timeout = jiffies +
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msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
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while ((tx_bytes > 0 || rx_bytes > 0) &&
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time_before(jiffies, timeout)) {
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unsigned int tx_count, rx_count;
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if (tx_bytes >= 4)
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tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
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else
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tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
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if (rx_bytes >= 4)
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rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
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else
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rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
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tx_buf += tx_count;
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rx_buf += rx_count;
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tx_bytes -= tx_count;
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rx_bytes -= rx_count;
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cpu_relax();
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}
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if (rx_bytes > 0 || tx_bytes > 0) {
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dev_err(spfi->dev, "PIO transfer timed out\n");
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spfi_reset(spfi);
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return -ETIMEDOUT;
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}
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if (tx_buf)
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spfi_flush_tx_fifo(spfi);
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spfi_stop(spfi);
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return 0;
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}
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static void img_spfi_dma_rx_cb(void *data)
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{
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struct img_spfi *spfi = data;
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unsigned long flags;
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spin_lock_irqsave(&spfi->lock, flags);
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spfi->rx_dma_busy = false;
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if (!spfi->tx_dma_busy) {
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spfi_stop(spfi);
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spi_finalize_current_transfer(spfi->master);
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}
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spin_unlock_irqrestore(&spfi->lock, flags);
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}
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static void img_spfi_dma_tx_cb(void *data)
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{
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struct img_spfi *spfi = data;
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unsigned long flags;
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spfi_flush_tx_fifo(spfi);
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spin_lock_irqsave(&spfi->lock, flags);
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spfi->tx_dma_busy = false;
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if (!spfi->rx_dma_busy) {
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spfi_stop(spfi);
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spi_finalize_current_transfer(spfi->master);
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}
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spin_unlock_irqrestore(&spfi->lock, flags);
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}
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static int img_spfi_start_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct img_spfi *spfi = spi_master_get_devdata(spi->master);
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struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
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struct dma_slave_config rxconf, txconf;
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spfi->rx_dma_busy = false;
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spfi->tx_dma_busy = false;
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if (xfer->rx_buf) {
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rxconf.direction = DMA_DEV_TO_MEM;
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if (xfer->len % 4 == 0) {
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rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
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rxconf.src_addr_width = 4;
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rxconf.src_maxburst = 4;
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} else {
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rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
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rxconf.src_addr_width = 1;
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rxconf.src_maxburst = 4;
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}
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dmaengine_slave_config(spfi->rx_ch, &rxconf);
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rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
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xfer->rx_sg.nents,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!rxdesc)
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goto stop_dma;
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rxdesc->callback = img_spfi_dma_rx_cb;
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rxdesc->callback_param = spfi;
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}
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if (xfer->tx_buf) {
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txconf.direction = DMA_MEM_TO_DEV;
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if (xfer->len % 4 == 0) {
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txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
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txconf.dst_addr_width = 4;
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txconf.dst_maxburst = 4;
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} else {
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txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
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txconf.dst_addr_width = 1;
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txconf.dst_maxburst = 4;
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}
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dmaengine_slave_config(spfi->tx_ch, &txconf);
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txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
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xfer->tx_sg.nents,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT);
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if (!txdesc)
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goto stop_dma;
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txdesc->callback = img_spfi_dma_tx_cb;
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txdesc->callback_param = spfi;
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}
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if (xfer->rx_buf) {
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spfi->rx_dma_busy = true;
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(spfi->rx_ch);
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}
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spfi_start(spfi);
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if (xfer->tx_buf) {
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spfi->tx_dma_busy = true;
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dmaengine_submit(txdesc);
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dma_async_issue_pending(spfi->tx_ch);
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}
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return 1;
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stop_dma:
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dmaengine_terminate_all(spfi->rx_ch);
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dmaengine_terminate_all(spfi->tx_ch);
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return -EIO;
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}
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static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct img_spfi *spfi = spi_master_get_devdata(spi->master);
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u32 val, div;
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/*
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* output = spfi_clk * (BITCLK / 512), where BITCLK must be a
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* power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits)
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*/
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div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz);
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div = clamp(512 / (1 << get_count_order(div)), 1, 255);
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val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
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val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
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SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
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val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
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spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
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val = spfi_readl(spfi, SPFI_CONTROL);
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val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
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if (xfer->tx_buf)
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val |= SPFI_CONTROL_SEND_DMA;
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if (xfer->rx_buf)
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val |= SPFI_CONTROL_GET_DMA;
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val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
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if (xfer->tx_nbits == SPI_NBITS_DUAL &&
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xfer->rx_nbits == SPI_NBITS_DUAL)
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val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
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else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
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xfer->rx_nbits == SPI_NBITS_QUAD)
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val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
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val &= ~SPFI_CONTROL_CONTINUE;
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if (!xfer->cs_change && !list_is_last(&xfer->transfer_list,
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&master->cur_msg->transfers))
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val |= SPFI_CONTROL_CONTINUE;
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spfi_writel(spfi, val, SPFI_CONTROL);
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val = spfi_readl(spfi, SPFI_PORT_STATE);
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if (spi->mode & SPI_CPHA)
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val |= SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
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else
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val &= ~SPFI_PORT_STATE_CK_PHASE(spi->chip_select);
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if (spi->mode & SPI_CPOL)
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val |= SPFI_PORT_STATE_CK_POL(spi->chip_select);
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else
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val &= ~SPFI_PORT_STATE_CK_POL(spi->chip_select);
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spfi_writel(spfi, val, SPFI_PORT_STATE);
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spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
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SPFI_TRANSACTION);
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}
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static int img_spfi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct img_spfi *spfi = spi_master_get_devdata(spi->master);
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bool dma_reset = false;
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unsigned long flags;
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int ret;
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if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
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dev_err(spfi->dev,
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"Transfer length (%d) is greater than the max supported (%d)",
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xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
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return -EINVAL;
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}
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/*
|
|
* Stop all DMA and reset the controller if the previous transaction
|
|
* timed-out and never completed it's DMA.
|
|
*/
|
|
spin_lock_irqsave(&spfi->lock, flags);
|
|
if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
|
|
dev_err(spfi->dev, "SPI DMA still busy\n");
|
|
dma_reset = true;
|
|
}
|
|
spin_unlock_irqrestore(&spfi->lock, flags);
|
|
|
|
if (dma_reset) {
|
|
dmaengine_terminate_all(spfi->tx_ch);
|
|
dmaengine_terminate_all(spfi->rx_ch);
|
|
spfi_reset(spfi);
|
|
}
|
|
|
|
img_spfi_config(master, spi, xfer);
|
|
if (master->can_dma && master->can_dma(master, spi, xfer))
|
|
ret = img_spfi_start_dma(master, spi, xfer);
|
|
else
|
|
ret = img_spfi_start_pio(master, spi, xfer);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void img_spfi_set_cs(struct spi_device *spi, bool enable)
|
|
{
|
|
struct img_spfi *spfi = spi_master_get_devdata(spi->master);
|
|
u32 val;
|
|
|
|
val = spfi_readl(spfi, SPFI_PORT_STATE);
|
|
val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT);
|
|
val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
|
|
spfi_writel(spfi, val, SPFI_PORT_STATE);
|
|
}
|
|
|
|
static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
if (xfer->len > SPFI_32BIT_FIFO_SIZE)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static irqreturn_t img_spfi_irq(int irq, void *dev_id)
|
|
{
|
|
struct img_spfi *spfi = (struct img_spfi *)dev_id;
|
|
u32 status;
|
|
|
|
status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
|
|
if (status & SPFI_INTERRUPT_IACCESS) {
|
|
spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
|
|
dev_err(spfi->dev, "Illegal access interrupt");
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static int img_spfi_probe(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master;
|
|
struct img_spfi *spfi;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
spfi = spi_master_get_devdata(master);
|
|
spfi->dev = &pdev->dev;
|
|
spfi->master = master;
|
|
spin_lock_init(&spfi->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
spfi->regs = devm_ioremap_resource(spfi->dev, res);
|
|
if (IS_ERR(spfi->regs)) {
|
|
ret = PTR_ERR(spfi->regs);
|
|
goto put_spi;
|
|
}
|
|
spfi->phys = res->start;
|
|
|
|
spfi->irq = platform_get_irq(pdev, 0);
|
|
if (spfi->irq < 0) {
|
|
ret = spfi->irq;
|
|
goto put_spi;
|
|
}
|
|
ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
|
|
IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
|
|
if (ret)
|
|
goto put_spi;
|
|
|
|
spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
|
|
if (IS_ERR(spfi->sys_clk)) {
|
|
ret = PTR_ERR(spfi->sys_clk);
|
|
goto put_spi;
|
|
}
|
|
spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
|
|
if (IS_ERR(spfi->spfi_clk)) {
|
|
ret = PTR_ERR(spfi->spfi_clk);
|
|
goto put_spi;
|
|
}
|
|
|
|
ret = clk_prepare_enable(spfi->sys_clk);
|
|
if (ret)
|
|
goto put_spi;
|
|
ret = clk_prepare_enable(spfi->spfi_clk);
|
|
if (ret)
|
|
goto disable_pclk;
|
|
|
|
spfi_reset(spfi);
|
|
/*
|
|
* Only enable the error (IACCESS) interrupt. In PIO mode we'll
|
|
* poll the status of the FIFOs.
|
|
*/
|
|
spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
|
|
|
|
master->auto_runtime_pm = true;
|
|
master->bus_num = pdev->id;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
|
|
if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
|
|
master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
|
|
master->num_chipselect = 5;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
|
|
master->max_speed_hz = clk_get_rate(spfi->spfi_clk);
|
|
master->min_speed_hz = master->max_speed_hz / 512;
|
|
|
|
master->set_cs = img_spfi_set_cs;
|
|
master->transfer_one = img_spfi_transfer_one;
|
|
|
|
spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
|
|
spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
|
|
if (!spfi->tx_ch || !spfi->rx_ch) {
|
|
if (spfi->tx_ch)
|
|
dma_release_channel(spfi->tx_ch);
|
|
if (spfi->rx_ch)
|
|
dma_release_channel(spfi->rx_ch);
|
|
dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
|
|
} else {
|
|
master->dma_tx = spfi->tx_ch;
|
|
master->dma_rx = spfi->rx_ch;
|
|
master->can_dma = img_spfi_can_dma;
|
|
}
|
|
|
|
pm_runtime_set_active(spfi->dev);
|
|
pm_runtime_enable(spfi->dev);
|
|
|
|
ret = devm_spi_register_master(spfi->dev, master);
|
|
if (ret)
|
|
goto disable_pm;
|
|
|
|
return 0;
|
|
|
|
disable_pm:
|
|
pm_runtime_disable(spfi->dev);
|
|
if (spfi->rx_ch)
|
|
dma_release_channel(spfi->rx_ch);
|
|
if (spfi->tx_ch)
|
|
dma_release_channel(spfi->tx_ch);
|
|
clk_disable_unprepare(spfi->spfi_clk);
|
|
disable_pclk:
|
|
clk_disable_unprepare(spfi->sys_clk);
|
|
put_spi:
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int img_spfi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct img_spfi *spfi = spi_master_get_devdata(master);
|
|
|
|
if (spfi->tx_ch)
|
|
dma_release_channel(spfi->tx_ch);
|
|
if (spfi->rx_ch)
|
|
dma_release_channel(spfi->rx_ch);
|
|
|
|
pm_runtime_disable(spfi->dev);
|
|
if (!pm_runtime_status_suspended(spfi->dev)) {
|
|
clk_disable_unprepare(spfi->spfi_clk);
|
|
clk_disable_unprepare(spfi->sys_clk);
|
|
}
|
|
|
|
spi_master_put(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int img_spfi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct img_spfi *spfi = spi_master_get_devdata(master);
|
|
|
|
clk_disable_unprepare(spfi->spfi_clk);
|
|
clk_disable_unprepare(spfi->sys_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int img_spfi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct img_spfi *spfi = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(spfi->sys_clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_prepare_enable(spfi->spfi_clk);
|
|
if (ret) {
|
|
clk_disable_unprepare(spfi->sys_clk);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int img_spfi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
return spi_master_suspend(master);
|
|
}
|
|
|
|
static int img_spfi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct img_spfi *spfi = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret)
|
|
return ret;
|
|
spfi_reset(spfi);
|
|
pm_runtime_put(dev);
|
|
|
|
return spi_master_resume(master);
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct dev_pm_ops img_spfi_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
|
|
NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
|
|
};
|
|
|
|
static const struct of_device_id img_spfi_of_match[] = {
|
|
{ .compatible = "img,spfi", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, img_spfi_of_match);
|
|
|
|
static struct platform_driver img_spfi_driver = {
|
|
.driver = {
|
|
.name = "img-spfi",
|
|
.pm = &img_spfi_pm_ops,
|
|
.of_match_table = of_match_ptr(img_spfi_of_match),
|
|
},
|
|
.probe = img_spfi_probe,
|
|
.remove = img_spfi_remove,
|
|
};
|
|
module_platform_driver(img_spfi_driver);
|
|
|
|
MODULE_DESCRIPTION("IMG SPFI controller driver");
|
|
MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
|
|
MODULE_LICENSE("GPL v2");
|