![Daniel Vetter](/assets/img/avatar_default.png)
Like before add a parameter mappable (also to gem_object_pin) and set it depending upon the context. Only bos that are brought into the gtt due to an execbuffer call can be put into the unmappable part of the gtt, everything else (especially pinned objects) need to be put into the mappable part of the gtt. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
1306 lines
39 KiB
C
1306 lines
39 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <drm/intel-gtt.h>
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
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#define DRIVER_NAME "i915"
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#define DRIVER_DESC "Intel Graphics"
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#define DRIVER_DATE "20080730"
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enum pipe {
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PIPE_A = 0,
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PIPE_B,
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};
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enum plane {
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PLANE_A = 0,
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PLANE_B,
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};
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#define I915_NUM_PIPE 2
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#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
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/* Interface history:
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*
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* 1.1: Original.
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* 1.2: Add Power Management
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* 1.3: Add vblank support
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* 1.4: Fix cmdbuffer path, add heap destroy
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* 1.5: Add vblank pipe configuration
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* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
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* - Support vertical blank on secondary display pipe
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 6
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#define DRIVER_PATCHLEVEL 0
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#define WATCH_COHERENCY 0
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#define WATCH_EXEC 0
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#define WATCH_RELOC 0
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#define WATCH_LISTS 0
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#define WATCH_PWRITE 0
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#define I915_GEM_PHYS_CURSOR_0 1
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#define I915_GEM_PHYS_CURSOR_1 2
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#define I915_GEM_PHYS_OVERLAY_REGS 3
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#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
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struct drm_i915_gem_phys_object {
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int id;
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struct page **page_list;
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drm_dma_handle_t *handle;
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struct drm_gem_object *cur_obj;
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};
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struct mem_block {
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struct mem_block *next;
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struct mem_block *prev;
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int start;
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int size;
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struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
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};
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struct opregion_header;
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struct opregion_acpi;
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struct opregion_swsci;
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struct opregion_asle;
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struct intel_opregion {
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struct opregion_header *header;
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struct opregion_acpi *acpi;
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struct opregion_swsci *swsci;
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struct opregion_asle *asle;
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void *vbt;
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};
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#define OPREGION_SIZE (8*1024)
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struct intel_overlay;
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struct intel_overlay_error_state;
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struct drm_i915_master_private {
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drm_local_map_t *sarea;
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struct _drm_i915_sarea *sarea_priv;
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};
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#define I915_FENCE_REG_NONE -1
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struct drm_i915_fence_reg {
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struct drm_gem_object *obj;
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struct list_head lru_list;
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bool gpu;
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};
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struct sdvo_device_mapping {
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u8 initialized;
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u8 dvo_port;
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u8 slave_addr;
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u8 dvo_wiring;
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u8 i2c_pin;
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u8 i2c_speed;
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u8 ddc_pin;
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};
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struct drm_i915_error_state {
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u32 eir;
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u32 pgtbl_er;
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u32 pipeastat;
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u32 pipebstat;
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u32 ipeir;
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u32 ipehr;
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u32 instdone;
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u32 acthd;
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u32 instpm;
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u32 instps;
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u32 instdone1;
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u32 seqno;
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u64 bbaddr;
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struct timeval time;
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struct drm_i915_error_object {
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int page_count;
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u32 gtt_offset;
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u32 *pages[0];
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} *ringbuffer, *batchbuffer[2];
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struct drm_i915_error_buffer {
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size_t size;
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u32 name;
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u32 seqno;
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u32 gtt_offset;
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u32 read_domains;
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u32 write_domain;
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u32 fence_reg;
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s32 pinned:2;
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u32 tiling:2;
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u32 dirty:1;
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u32 purgeable:1;
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} *active_bo;
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u32 active_bo_count;
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struct intel_overlay_error_state *overlay;
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};
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struct drm_i915_display_funcs {
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void (*dpms)(struct drm_crtc *crtc, int mode);
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bool (*fbc_enabled)(struct drm_device *dev);
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void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
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void (*disable_fbc)(struct drm_device *dev);
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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void (*update_wm)(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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/* display clock increase/decrease */
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/* pll clock increase/decrease */
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/* clock gating init */
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};
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struct intel_device_info {
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u8 gen;
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u8 is_mobile : 1;
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u8 is_i85x : 1;
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u8 is_i915g : 1;
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u8 is_i945gm : 1;
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u8 is_g33 : 1;
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u8 need_gfx_hws : 1;
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u8 is_g4x : 1;
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u8 is_pineview : 1;
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u8 is_broadwater : 1;
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u8 is_crestline : 1;
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u8 has_fbc : 1;
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u8 has_rc6 : 1;
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u8 has_pipe_cxsr : 1;
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u8 has_hotplug : 1;
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u8 cursor_needs_physical : 1;
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u8 has_overlay : 1;
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u8 overlay_needs_physical : 1;
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u8 supports_tv : 1;
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u8 has_bsd_ring : 1;
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u8 has_blt_ring : 1;
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};
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enum no_fbc_reason {
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FBC_NO_OUTPUT, /* no outputs enabled to compress */
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FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
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FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
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FBC_MODE_TOO_LARGE, /* mode too large for compression */
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FBC_BAD_PLANE, /* fbc not supported on plane */
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FBC_NOT_TILED, /* buffer not tiled */
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FBC_MULTIPLE_PIPES, /* more than one pipe active */
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};
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enum intel_pch {
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PCH_IBX, /* Ibexpeak PCH */
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PCH_CPT, /* Cougarpoint PCH */
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};
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#define QUIRK_PIPEA_FORCE (1<<0)
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struct intel_fbdev;
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typedef struct drm_i915_private {
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struct drm_device *dev;
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const struct intel_device_info *info;
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int has_gem;
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void __iomem *regs;
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struct intel_gmbus {
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struct i2c_adapter adapter;
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struct i2c_adapter *force_bit;
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u32 reg0;
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} *gmbus;
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struct pci_dev *bridge_dev;
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struct intel_ring_buffer render_ring;
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struct intel_ring_buffer bsd_ring;
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struct intel_ring_buffer blt_ring;
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uint32_t next_seqno;
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drm_dma_handle_t *status_page_dmah;
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void *seqno_page;
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dma_addr_t dma_status_page;
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uint32_t counter;
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unsigned int seqno_gfx_addr;
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drm_local_map_t hws_map;
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struct drm_gem_object *seqno_obj;
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struct drm_gem_object *pwrctx;
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struct drm_gem_object *renderctx;
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struct resource mch_res;
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unsigned int cpp;
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int back_offset;
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int front_offset;
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int current_page;
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int page_flipping;
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#define I915_DEBUG_READ (1<<0)
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#define I915_DEBUG_WRITE (1<<1)
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unsigned long debug_flags;
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wait_queue_head_t irq_queue;
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atomic_t irq_received;
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/** Protects user_irq_refcount and irq_mask_reg */
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spinlock_t user_irq_lock;
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u32 trace_irq_seqno;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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u32 irq_mask_reg;
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u32 pipestat[2];
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/** splitted irq regs for graphics and display engine on Ironlake,
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irq_mask_reg is still used for display irq. */
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u32 gt_irq_mask_reg;
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u32 gt_irq_enable_reg;
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u32 de_irq_enable_reg;
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u32 pch_irq_mask_reg;
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u32 pch_irq_enable_reg;
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u32 hotplug_supported_mask;
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struct work_struct hotplug_work;
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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struct mem_block *agp_heap;
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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int vblank_pipe;
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int num_pipe;
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/* For hangcheck timer */
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#define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
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struct timer_list hangcheck_timer;
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int hangcheck_count;
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uint32_t last_acthd;
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uint32_t last_instdone;
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uint32_t last_instdone1;
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unsigned long cfb_size;
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unsigned long cfb_pitch;
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unsigned long cfb_offset;
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int cfb_fence;
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int cfb_plane;
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int cfb_y;
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int irq_enabled;
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struct intel_opregion opregion;
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/* overlay */
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struct intel_overlay *overlay;
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/* LVDS info */
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int backlight_level; /* restore backlight to this value */
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struct drm_display_mode *panel_fixed_mode;
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struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
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struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
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/* Feature bits from the VBIOS */
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unsigned int int_tv_support:1;
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unsigned int lvds_dither:1;
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unsigned int lvds_vbt:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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int lvds_ssc_freq;
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struct {
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int rate;
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int lanes;
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int preemphasis;
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int vswing;
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bool initialized;
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bool support;
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int bpp;
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struct edp_power_seq pps;
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} edp;
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bool no_aux_handshake;
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struct notifier_block lid_notifier;
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int crt_ddc_pin;
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struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
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int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
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int num_fence_regs; /* 8 on pre-965, 16 otherwise */
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unsigned int fsb_freq, mem_freq, is_ddr3;
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spinlock_t error_lock;
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struct drm_i915_error_state *first_error;
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struct work_struct error_work;
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struct completion error_completion;
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struct workqueue_struct *wq;
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/* Display functions */
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struct drm_i915_display_funcs display;
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/* PCH chipset type */
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enum intel_pch pch_type;
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unsigned long quirks;
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/* Register state */
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bool modeset_on_lid;
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u8 saveLBB;
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 saveHWS;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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u32 savePIPEBSRC;
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u32 saveFPA0;
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u32 saveFPA1;
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u32 saveDPLL_A;
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u32 saveDPLL_A_MD;
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u32 saveHTOTAL_A;
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u32 saveHBLANK_A;
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u32 saveHSYNC_A;
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u32 saveVTOTAL_A;
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u32 saveVBLANK_A;
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u32 saveVSYNC_A;
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u32 saveBCLRPAT_A;
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u32 saveTRANSACONF;
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u32 saveTRANS_HTOTAL_A;
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u32 saveTRANS_HBLANK_A;
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u32 saveTRANS_HSYNC_A;
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u32 saveTRANS_VTOTAL_A;
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u32 saveTRANS_VBLANK_A;
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u32 saveTRANS_VSYNC_A;
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u32 savePIPEASTAT;
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u32 saveDSPASTRIDE;
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u32 saveDSPASIZE;
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u32 saveDSPAPOS;
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u32 saveDSPAADDR;
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u32 saveDSPASURF;
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u32 saveDSPATILEOFF;
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u32 savePFIT_PGM_RATIOS;
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u32 saveBLC_HIST_CTL;
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u32 saveBLC_PWM_CTL;
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u32 saveBLC_PWM_CTL2;
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u32 saveBLC_CPU_PWM_CTL;
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u32 saveBLC_CPU_PWM_CTL2;
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u32 saveFPB0;
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u32 saveFPB1;
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u32 saveDPLL_B;
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u32 saveDPLL_B_MD;
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u32 saveHTOTAL_B;
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u32 saveHBLANK_B;
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u32 saveHSYNC_B;
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u32 saveVTOTAL_B;
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u32 saveVBLANK_B;
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u32 saveVSYNC_B;
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u32 saveBCLRPAT_B;
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u32 saveTRANSBCONF;
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u32 saveTRANS_HTOTAL_B;
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u32 saveTRANS_HBLANK_B;
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u32 saveTRANS_HSYNC_B;
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u32 saveTRANS_VTOTAL_B;
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u32 saveTRANS_VBLANK_B;
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u32 saveTRANS_VSYNC_B;
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u32 savePIPEBSTAT;
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u32 saveDSPBSTRIDE;
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u32 saveDSPBSIZE;
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u32 saveDSPBPOS;
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u32 saveDSPBADDR;
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u32 saveDSPBSURF;
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u32 saveDSPBTILEOFF;
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u32 saveVGA0;
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u32 saveVGA1;
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u32 saveVGA_PD;
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u32 saveVGACNTRL;
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u32 saveADPA;
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u32 saveLVDS;
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u32 savePP_ON_DELAYS;
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u32 savePP_OFF_DELAYS;
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u32 saveDVOA;
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u32 saveDVOB;
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u32 saveDVOC;
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u32 savePP_ON;
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u32 savePP_OFF;
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u32 savePP_CONTROL;
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u32 savePP_DIVISOR;
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u32 savePFIT_CONTROL;
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u32 save_palette_a[256];
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u32 save_palette_b[256];
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u32 saveDPFC_CB_BASE;
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u32 saveFBC_CFB_BASE;
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u32 saveFBC_LL_BASE;
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u32 saveFBC_CONTROL;
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u32 saveFBC_CONTROL2;
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u32 saveIER;
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u32 saveIIR;
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u32 saveIMR;
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u32 saveDEIER;
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u32 saveDEIMR;
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u32 saveGTIER;
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u32 saveGTIMR;
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u32 saveFDI_RXA_IMR;
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u32 saveFDI_RXB_IMR;
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u32 saveCACHE_MODE_0;
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u32 saveMI_ARB_STATE;
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u32 saveSWF0[16];
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u32 saveSWF1[16];
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u32 saveSWF2[3];
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u8 saveMSR;
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u8 saveSR[8];
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u8 saveGR[25];
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u8 saveAR_INDEX;
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u8 saveAR[21];
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u8 saveDACMASK;
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u8 saveCR[37];
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uint64_t saveFENCE[16];
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u32 saveCURACNTR;
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u32 saveCURAPOS;
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u32 saveCURABASE;
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u32 saveCURBCNTR;
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u32 saveCURBPOS;
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u32 saveCURBBASE;
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u32 saveCURSIZE;
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u32 saveDP_B;
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u32 saveDP_C;
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u32 saveDP_D;
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u32 savePIPEA_GMCH_DATA_M;
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u32 savePIPEB_GMCH_DATA_M;
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u32 savePIPEA_GMCH_DATA_N;
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u32 savePIPEB_GMCH_DATA_N;
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u32 savePIPEA_DP_LINK_M;
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u32 savePIPEB_DP_LINK_M;
|
|
u32 savePIPEA_DP_LINK_N;
|
|
u32 savePIPEB_DP_LINK_N;
|
|
u32 saveFDI_RXA_CTL;
|
|
u32 saveFDI_TXA_CTL;
|
|
u32 saveFDI_RXB_CTL;
|
|
u32 saveFDI_TXB_CTL;
|
|
u32 savePFA_CTL_1;
|
|
u32 savePFB_CTL_1;
|
|
u32 savePFA_WIN_SZ;
|
|
u32 savePFB_WIN_SZ;
|
|
u32 savePFA_WIN_POS;
|
|
u32 savePFB_WIN_POS;
|
|
u32 savePCH_DREF_CONTROL;
|
|
u32 saveDISP_ARB_CTL;
|
|
u32 savePIPEA_DATA_M1;
|
|
u32 savePIPEA_DATA_N1;
|
|
u32 savePIPEA_LINK_M1;
|
|
u32 savePIPEA_LINK_N1;
|
|
u32 savePIPEB_DATA_M1;
|
|
u32 savePIPEB_DATA_N1;
|
|
u32 savePIPEB_LINK_M1;
|
|
u32 savePIPEB_LINK_N1;
|
|
u32 saveMCHBAR_RENDER_STANDBY;
|
|
|
|
struct {
|
|
/** Bridge to intel-gtt-ko */
|
|
struct intel_gtt *gtt;
|
|
/** Memory allocator for GTT stolen memory */
|
|
struct drm_mm vram;
|
|
/** Memory allocator for GTT */
|
|
struct drm_mm gtt_space;
|
|
/** End of mappable part of GTT */
|
|
unsigned long gtt_mappable_end;
|
|
|
|
struct io_mapping *gtt_mapping;
|
|
int gtt_mtrr;
|
|
|
|
/**
|
|
* Membership on list of all loaded devices, used to evict
|
|
* inactive buffers under memory pressure.
|
|
*
|
|
* Modifications should only be done whilst holding the
|
|
* shrink_list_lock spinlock.
|
|
*/
|
|
struct list_head shrink_list;
|
|
|
|
/**
|
|
* List of objects currently involved in rendering.
|
|
*
|
|
* Includes buffers having the contents of their GPU caches
|
|
* flushed, not necessarily primitives. last_rendering_seqno
|
|
* represents when the rendering involved will be completed.
|
|
*
|
|
* A reference is held on the buffer while on this list.
|
|
*/
|
|
struct list_head active_list;
|
|
|
|
/**
|
|
* List of objects which are not in the ringbuffer but which
|
|
* still have a write_domain which needs to be flushed before
|
|
* unbinding.
|
|
*
|
|
* last_rendering_seqno is 0 while an object is in this list.
|
|
*
|
|
* A reference is held on the buffer while on this list.
|
|
*/
|
|
struct list_head flushing_list;
|
|
|
|
/**
|
|
* LRU list of objects which are not in the ringbuffer and
|
|
* are ready to unbind, but are still in the GTT.
|
|
*
|
|
* last_rendering_seqno is 0 while an object is in this list.
|
|
*
|
|
* A reference is not held on the buffer while on this list,
|
|
* as merely being GTT-bound shouldn't prevent its being
|
|
* freed, and we'll pull it off the list in the free path.
|
|
*/
|
|
struct list_head inactive_list;
|
|
|
|
/**
|
|
* LRU list of objects which are not in the ringbuffer but
|
|
* are still pinned in the GTT.
|
|
*/
|
|
struct list_head pinned_list;
|
|
|
|
/** LRU list of objects with fence regs on them. */
|
|
struct list_head fence_list;
|
|
|
|
/**
|
|
* List of objects currently pending being freed.
|
|
*
|
|
* These objects are no longer in use, but due to a signal
|
|
* we were prevented from freeing them at the appointed time.
|
|
*/
|
|
struct list_head deferred_free_list;
|
|
|
|
/**
|
|
* We leave the user IRQ off as much as possible,
|
|
* but this means that requests will finish and never
|
|
* be retired once the system goes idle. Set a timer to
|
|
* fire periodically while the ring is running. When it
|
|
* fires, go retire requests.
|
|
*/
|
|
struct delayed_work retire_work;
|
|
|
|
/**
|
|
* Flag if the X Server, and thus DRM, is not currently in
|
|
* control of the device.
|
|
*
|
|
* This is set between LeaveVT and EnterVT. It needs to be
|
|
* replaced with a semaphore. It also needs to be
|
|
* transitioned away from for kernel modesetting.
|
|
*/
|
|
int suspended;
|
|
|
|
/**
|
|
* Flag if the hardware appears to be wedged.
|
|
*
|
|
* This is set when attempts to idle the device timeout.
|
|
* It prevents command submission from occuring and makes
|
|
* every pending request fail
|
|
*/
|
|
atomic_t wedged;
|
|
|
|
/** Bit 6 swizzling required for X tiling */
|
|
uint32_t bit_6_swizzle_x;
|
|
/** Bit 6 swizzling required for Y tiling */
|
|
uint32_t bit_6_swizzle_y;
|
|
|
|
/* storage for physical objects */
|
|
struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
|
|
|
|
uint32_t flush_rings;
|
|
|
|
/* accounting, useful for userland debugging */
|
|
size_t object_memory;
|
|
size_t pin_memory;
|
|
size_t gtt_memory;
|
|
size_t gtt_total;
|
|
u32 object_count;
|
|
u32 pin_count;
|
|
u32 gtt_count;
|
|
} mm;
|
|
struct sdvo_device_mapping sdvo_mappings[2];
|
|
/* indicate whether the LVDS_BORDER should be enabled or not */
|
|
unsigned int lvds_border_bits;
|
|
/* Panel fitter placement and size for Ironlake+ */
|
|
u32 pch_pf_pos, pch_pf_size;
|
|
|
|
struct drm_crtc *plane_to_crtc_mapping[2];
|
|
struct drm_crtc *pipe_to_crtc_mapping[2];
|
|
wait_queue_head_t pending_flip_queue;
|
|
bool flip_pending_is_done;
|
|
|
|
/* Reclocking support */
|
|
bool render_reclock_avail;
|
|
bool lvds_downclock_avail;
|
|
/* indicates the reduced downclock for LVDS*/
|
|
int lvds_downclock;
|
|
struct work_struct idle_work;
|
|
struct timer_list idle_timer;
|
|
bool busy;
|
|
u16 orig_clock;
|
|
int child_dev_num;
|
|
struct child_device_config *child_dev;
|
|
struct drm_connector *int_lvds_connector;
|
|
|
|
bool mchbar_need_disable;
|
|
|
|
u8 cur_delay;
|
|
u8 min_delay;
|
|
u8 max_delay;
|
|
u8 fmax;
|
|
u8 fstart;
|
|
|
|
u64 last_count1;
|
|
unsigned long last_time1;
|
|
u64 last_count2;
|
|
struct timespec last_time2;
|
|
unsigned long gfx_power;
|
|
int c_m;
|
|
int r_t;
|
|
u8 corr;
|
|
spinlock_t *mchdev_lock;
|
|
|
|
enum no_fbc_reason no_fbc_reason;
|
|
|
|
struct drm_mm_node *compressed_fb;
|
|
struct drm_mm_node *compressed_llb;
|
|
|
|
unsigned long last_gpu_reset;
|
|
|
|
/* list of fbdev register on this device */
|
|
struct intel_fbdev *fbdev;
|
|
} drm_i915_private_t;
|
|
|
|
/** driver private structure attached to each drm_gem_object */
|
|
struct drm_i915_gem_object {
|
|
struct drm_gem_object base;
|
|
|
|
/** Current space allocated to this object in the GTT, if any. */
|
|
struct drm_mm_node *gtt_space;
|
|
|
|
/** This object's place on the active/flushing/inactive lists */
|
|
struct list_head ring_list;
|
|
struct list_head mm_list;
|
|
/** This object's place on GPU write list */
|
|
struct list_head gpu_write_list;
|
|
/** This object's place on eviction list */
|
|
struct list_head evict_list;
|
|
|
|
/**
|
|
* This is set if the object is on the active or flushing lists
|
|
* (has pending rendering), and is not set if it's on inactive (ready
|
|
* to be unbound).
|
|
*/
|
|
unsigned int active : 1;
|
|
|
|
/**
|
|
* This is set if the object has been written to since last bound
|
|
* to the GTT
|
|
*/
|
|
unsigned int dirty : 1;
|
|
|
|
/**
|
|
* Fence register bits (if any) for this object. Will be set
|
|
* as needed when mapped into the GTT.
|
|
* Protected by dev->struct_mutex.
|
|
*
|
|
* Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
|
|
*/
|
|
signed int fence_reg : 5;
|
|
|
|
/**
|
|
* Used for checking the object doesn't appear more than once
|
|
* in an execbuffer object list.
|
|
*/
|
|
unsigned int in_execbuffer : 1;
|
|
|
|
/**
|
|
* Advice: are the backing pages purgeable?
|
|
*/
|
|
unsigned int madv : 2;
|
|
|
|
/**
|
|
* Refcount for the pages array. With the current locking scheme, there
|
|
* are at most two concurrent users: Binding a bo to the gtt and
|
|
* pwrite/pread using physical addresses. So two bits for a maximum
|
|
* of two users are enough.
|
|
*/
|
|
unsigned int pages_refcount : 2;
|
|
#define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
|
|
|
|
/**
|
|
* Current tiling mode for the object.
|
|
*/
|
|
unsigned int tiling_mode : 2;
|
|
|
|
/** How many users have pinned this object in GTT space. The following
|
|
* users can each hold at most one reference: pwrite/pread, pin_ioctl
|
|
* (via user_pin_count), execbuffer (objects are not allowed multiple
|
|
* times for the same batchbuffer), and the framebuffer code. When
|
|
* switching/pageflipping, the framebuffer code has at most two buffers
|
|
* pinned per crtc.
|
|
*
|
|
* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
|
|
* bits with absolutely no headroom. So use 4 bits. */
|
|
unsigned int pin_count : 4;
|
|
#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
|
|
|
|
/** AGP memory structure for our GTT binding. */
|
|
DRM_AGP_MEM *agp_mem;
|
|
|
|
struct page **pages;
|
|
|
|
/**
|
|
* Current offset of the object in GTT space.
|
|
*
|
|
* This is the same as gtt_space->start
|
|
*/
|
|
uint32_t gtt_offset;
|
|
|
|
/* Which ring is refering to is this object */
|
|
struct intel_ring_buffer *ring;
|
|
|
|
/**
|
|
* Fake offset for use by mmap(2)
|
|
*/
|
|
uint64_t mmap_offset;
|
|
|
|
/** Breadcrumb of last rendering to the buffer. */
|
|
uint32_t last_rendering_seqno;
|
|
|
|
/** Current tiling stride for the object, if it's tiled. */
|
|
uint32_t stride;
|
|
|
|
/** Record of address bit 17 of each page at last unbind. */
|
|
unsigned long *bit_17;
|
|
|
|
/** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
|
|
uint32_t agp_type;
|
|
|
|
/**
|
|
* If present, while GEM_DOMAIN_CPU is in the read domain this array
|
|
* flags which individual pages are valid.
|
|
*/
|
|
uint8_t *page_cpu_valid;
|
|
|
|
/** User space pin count and filp owning the pin */
|
|
uint32_t user_pin_count;
|
|
struct drm_file *pin_filp;
|
|
|
|
/** for phy allocated objects */
|
|
struct drm_i915_gem_phys_object *phys_obj;
|
|
|
|
/**
|
|
* Number of crtcs where this object is currently the fb, but
|
|
* will be page flipped away on the next vblank. When it
|
|
* reaches 0, dev_priv->pending_flip_queue will be woken up.
|
|
*/
|
|
atomic_t pending_flip;
|
|
};
|
|
|
|
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
|
|
|
|
/**
|
|
* Request queue structure.
|
|
*
|
|
* The request queue allows us to note sequence numbers that have been emitted
|
|
* and may be associated with active buffers to be retired.
|
|
*
|
|
* By keeping this list, we can avoid having to do questionable
|
|
* sequence-number comparisons on buffer last_rendering_seqnos, and associate
|
|
* an emission time with seqnos for tracking how far ahead of the GPU we are.
|
|
*/
|
|
struct drm_i915_gem_request {
|
|
/** On Which ring this request was generated */
|
|
struct intel_ring_buffer *ring;
|
|
|
|
/** GEM sequence number associated with this request. */
|
|
uint32_t seqno;
|
|
|
|
/** Time at which this request was emitted, in jiffies. */
|
|
unsigned long emitted_jiffies;
|
|
|
|
/** global list entry for this request */
|
|
struct list_head list;
|
|
|
|
struct drm_i915_file_private *file_priv;
|
|
/** file_priv list entry for this request */
|
|
struct list_head client_list;
|
|
};
|
|
|
|
struct drm_i915_file_private {
|
|
struct {
|
|
struct spinlock lock;
|
|
struct list_head request_list;
|
|
} mm;
|
|
};
|
|
|
|
enum intel_chip_family {
|
|
CHIP_I8XX = 0x01,
|
|
CHIP_I9XX = 0x02,
|
|
CHIP_I915 = 0x04,
|
|
CHIP_I965 = 0x08,
|
|
};
|
|
|
|
extern struct drm_ioctl_desc i915_ioctls[];
|
|
extern int i915_max_ioctl;
|
|
extern unsigned int i915_fbpercrtc;
|
|
extern unsigned int i915_powersave;
|
|
extern unsigned int i915_lvds_downclock;
|
|
|
|
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
|
|
extern int i915_resume(struct drm_device *dev);
|
|
extern void i915_save_display(struct drm_device *dev);
|
|
extern void i915_restore_display(struct drm_device *dev);
|
|
extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
|
|
extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
|
|
|
|
/* i915_dma.c */
|
|
extern void i915_kernel_lost_context(struct drm_device * dev);
|
|
extern int i915_driver_load(struct drm_device *, unsigned long flags);
|
|
extern int i915_driver_unload(struct drm_device *);
|
|
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
|
|
extern void i915_driver_lastclose(struct drm_device * dev);
|
|
extern void i915_driver_preclose(struct drm_device *dev,
|
|
struct drm_file *file_priv);
|
|
extern void i915_driver_postclose(struct drm_device *dev,
|
|
struct drm_file *file_priv);
|
|
extern int i915_driver_device_is_agp(struct drm_device * dev);
|
|
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg);
|
|
extern int i915_emit_box(struct drm_device *dev,
|
|
struct drm_clip_rect *boxes,
|
|
int i, int DR1, int DR4);
|
|
extern int i915_reset(struct drm_device *dev, u8 flags);
|
|
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
|
|
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
|
|
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
|
|
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
|
|
|
|
|
|
/* i915_irq.c */
|
|
void i915_hangcheck_elapsed(unsigned long data);
|
|
extern int i915_irq_emit(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_irq_wait(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
|
|
extern void i915_enable_interrupt (struct drm_device *dev);
|
|
|
|
extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
|
|
extern void i915_driver_irq_preinstall(struct drm_device * dev);
|
|
extern int i915_driver_irq_postinstall(struct drm_device *dev);
|
|
extern void i915_driver_irq_uninstall(struct drm_device * dev);
|
|
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_enable_vblank(struct drm_device *dev, int crtc);
|
|
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
|
|
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
|
|
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
|
|
extern int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
|
extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
|
|
extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
|
|
u32 mask);
|
|
extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
|
|
u32 mask);
|
|
|
|
void
|
|
i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
|
|
|
|
void
|
|
i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
|
|
|
|
void intel_enable_asle (struct drm_device *dev);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
extern void i915_destroy_error_state(struct drm_device *dev);
|
|
#else
|
|
#define i915_destroy_error_state(x)
|
|
#endif
|
|
|
|
|
|
/* i915_mem.c */
|
|
extern int i915_mem_alloc(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_mem_free(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_mem_init_heap(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
extern void i915_mem_takedown(struct mem_block **heap);
|
|
extern void i915_mem_release(struct drm_device * dev,
|
|
struct drm_file *file_priv, struct mem_block *heap);
|
|
/* i915_gem.c */
|
|
int i915_gem_check_is_wedged(struct drm_device *dev);
|
|
int i915_gem_init_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_execbuffer(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_set_tiling(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_get_tiling(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
void i915_gem_load(struct drm_device *dev);
|
|
int i915_gem_init_object(struct drm_gem_object *obj);
|
|
struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
|
|
size_t size);
|
|
void i915_gem_free_object(struct drm_gem_object *obj);
|
|
int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
|
|
bool mappable);
|
|
void i915_gem_object_unpin(struct drm_gem_object *obj);
|
|
int i915_gem_object_unbind(struct drm_gem_object *obj);
|
|
void i915_gem_release_mmap(struct drm_gem_object *obj);
|
|
void i915_gem_lastclose(struct drm_device *dev);
|
|
|
|
/**
|
|
* Returns true if seq1 is later than seq2.
|
|
*/
|
|
static inline bool
|
|
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
|
|
{
|
|
return (int32_t)(seq1 - seq2) >= 0;
|
|
}
|
|
|
|
int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
|
|
bool interruptible);
|
|
int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
|
|
bool interruptible);
|
|
void i915_gem_retire_requests(struct drm_device *dev);
|
|
void i915_gem_reset(struct drm_device *dev);
|
|
void i915_gem_clflush_object(struct drm_gem_object *obj);
|
|
int i915_gem_object_set_domain(struct drm_gem_object *obj,
|
|
uint32_t read_domains,
|
|
uint32_t write_domain);
|
|
int i915_gem_init_ringbuffer(struct drm_device *dev);
|
|
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
|
|
int i915_gem_do_init(struct drm_device *dev, unsigned long start,
|
|
unsigned long end);
|
|
int i915_gpu_idle(struct drm_device *dev);
|
|
int i915_gem_idle(struct drm_device *dev);
|
|
int i915_add_request(struct drm_device *dev,
|
|
struct drm_file *file_priv,
|
|
struct drm_i915_gem_request *request,
|
|
struct intel_ring_buffer *ring);
|
|
int i915_do_wait_request(struct drm_device *dev,
|
|
uint32_t seqno,
|
|
bool interruptible,
|
|
struct intel_ring_buffer *ring);
|
|
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
|
|
int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
|
|
int write);
|
|
int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
|
|
bool pipelined);
|
|
int i915_gem_attach_phys_object(struct drm_device *dev,
|
|
struct drm_gem_object *obj,
|
|
int id,
|
|
int align);
|
|
void i915_gem_detach_phys_object(struct drm_device *dev,
|
|
struct drm_gem_object *obj);
|
|
void i915_gem_free_all_phys_object(struct drm_device *dev);
|
|
void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
|
|
|
|
void i915_gem_shrinker_init(void);
|
|
void i915_gem_shrinker_exit(void);
|
|
|
|
/* i915_gem_evict.c */
|
|
int i915_gem_evict_something(struct drm_device *dev, int min_size,
|
|
unsigned alignment, bool mappable);
|
|
int i915_gem_evict_everything(struct drm_device *dev);
|
|
int i915_gem_evict_inactive(struct drm_device *dev);
|
|
|
|
/* i915_gem_tiling.c */
|
|
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
|
|
void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
|
|
void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
|
|
bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
|
|
int tiling_mode);
|
|
bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
|
|
int tiling_mode);
|
|
|
|
/* i915_gem_debug.c */
|
|
void i915_gem_dump_object(struct drm_gem_object *obj, int len,
|
|
const char *where, uint32_t mark);
|
|
#if WATCH_LISTS
|
|
int i915_verify_lists(struct drm_device *dev);
|
|
#else
|
|
#define i915_verify_lists(dev) 0
|
|
#endif
|
|
void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
|
|
void i915_gem_dump_object(struct drm_gem_object *obj, int len,
|
|
const char *where, uint32_t mark);
|
|
|
|
/* i915_debugfs.c */
|
|
int i915_debugfs_init(struct drm_minor *minor);
|
|
void i915_debugfs_cleanup(struct drm_minor *minor);
|
|
|
|
/* i915_suspend.c */
|
|
extern int i915_save_state(struct drm_device *dev);
|
|
extern int i915_restore_state(struct drm_device *dev);
|
|
|
|
/* i915_suspend.c */
|
|
extern int i915_save_state(struct drm_device *dev);
|
|
extern int i915_restore_state(struct drm_device *dev);
|
|
|
|
/* intel_i2c.c */
|
|
extern int intel_setup_gmbus(struct drm_device *dev);
|
|
extern void intel_teardown_gmbus(struct drm_device *dev);
|
|
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
|
|
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
|
|
extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
|
|
{
|
|
return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
|
|
}
|
|
extern void intel_i2c_reset(struct drm_device *dev);
|
|
|
|
/* intel_opregion.c */
|
|
extern int intel_opregion_setup(struct drm_device *dev);
|
|
#ifdef CONFIG_ACPI
|
|
extern void intel_opregion_init(struct drm_device *dev);
|
|
extern void intel_opregion_fini(struct drm_device *dev);
|
|
extern void intel_opregion_asle_intr(struct drm_device *dev);
|
|
extern void intel_opregion_gse_intr(struct drm_device *dev);
|
|
extern void intel_opregion_enable_asle(struct drm_device *dev);
|
|
#else
|
|
static inline void intel_opregion_init(struct drm_device *dev) { return; }
|
|
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
|
|
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
|
|
static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
|
|
static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
|
|
#endif
|
|
|
|
/* intel_acpi.c */
|
|
#ifdef CONFIG_ACPI
|
|
extern void intel_register_dsm_handler(void);
|
|
extern void intel_unregister_dsm_handler(void);
|
|
#else
|
|
static inline void intel_register_dsm_handler(void) { return; }
|
|
static inline void intel_unregister_dsm_handler(void) { return; }
|
|
#endif /* CONFIG_ACPI */
|
|
|
|
/* modesetting */
|
|
extern void intel_modeset_init(struct drm_device *dev);
|
|
extern void intel_modeset_cleanup(struct drm_device *dev);
|
|
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
|
|
extern void i8xx_disable_fbc(struct drm_device *dev);
|
|
extern void g4x_disable_fbc(struct drm_device *dev);
|
|
extern void ironlake_disable_fbc(struct drm_device *dev);
|
|
extern void intel_disable_fbc(struct drm_device *dev);
|
|
extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
|
|
extern bool intel_fbc_enabled(struct drm_device *dev);
|
|
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
|
|
extern void intel_detect_pch (struct drm_device *dev);
|
|
extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
|
|
|
|
/* overlay */
|
|
#ifdef CONFIG_DEBUG_FS
|
|
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
|
|
extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
|
|
#endif
|
|
|
|
/**
|
|
* Lock test for when it's just for synchronization of ring access.
|
|
*
|
|
* In that case, we don't need to do it when GEM is initialized as nobody else
|
|
* has access to the ring.
|
|
*/
|
|
#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
|
|
if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
|
|
== NULL) \
|
|
LOCK_TEST_WITH_RETURN(dev, file_priv); \
|
|
} while (0)
|
|
|
|
static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
|
|
{
|
|
u32 val;
|
|
|
|
val = readl(dev_priv->regs + reg);
|
|
if (dev_priv->debug_flags & I915_DEBUG_READ)
|
|
printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
|
|
return val;
|
|
}
|
|
|
|
static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
|
|
u32 val)
|
|
{
|
|
writel(val, dev_priv->regs + reg);
|
|
if (dev_priv->debug_flags & I915_DEBUG_WRITE)
|
|
printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
|
|
}
|
|
|
|
#define I915_READ(reg) i915_read(dev_priv, (reg))
|
|
#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
|
|
#define I915_READ16(reg) readw(dev_priv->regs + (reg))
|
|
#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
|
|
#define I915_READ8(reg) readb(dev_priv->regs + (reg))
|
|
#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
|
|
#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
|
|
#define I915_READ64(reg) readq(dev_priv->regs + (reg))
|
|
#define POSTING_READ(reg) (void)I915_READ(reg)
|
|
#define POSTING_READ16(reg) (void)I915_READ16(reg)
|
|
|
|
#define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
|
|
I915_DEBUG_WRITE)
|
|
#define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
|
|
I915_DEBUG_WRITE))
|
|
|
|
#define BEGIN_LP_RING(n) \
|
|
intel_ring_begin(&dev_priv->render_ring, (n))
|
|
|
|
#define OUT_RING(x) \
|
|
intel_ring_emit(&dev_priv->render_ring, x)
|
|
|
|
#define ADVANCE_LP_RING() \
|
|
intel_ring_advance(&dev_priv->render_ring)
|
|
|
|
/**
|
|
* Reads a dword out of the status page, which is written to from the command
|
|
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
|
|
* MI_STORE_DATA_IMM.
|
|
*
|
|
* The following dwords have a reserved meaning:
|
|
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
|
|
* 0x04: ring 0 head pointer
|
|
* 0x05: ring 1 head pointer (915-class)
|
|
* 0x06: ring 2 head pointer (915-class)
|
|
* 0x10-0x1b: Context status DWords (GM45)
|
|
* 0x1f: Last written status offset. (GM45)
|
|
*
|
|
* The area from dword 0x20 to 0x3ff is available for driver usage.
|
|
*/
|
|
#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
|
|
(dev_priv->render_ring.status_page.page_addr))[reg])
|
|
#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
|
|
#define I915_GEM_HWS_INDEX 0x20
|
|
#define I915_BREADCRUMB_INDEX 0x21
|
|
|
|
#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
|
|
|
|
#define IS_I830(dev) ((dev)->pci_device == 0x3577)
|
|
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
|
|
#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
|
|
#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
|
|
#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
|
|
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
|
|
#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
|
|
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
|
|
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
|
|
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
|
|
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
|
|
#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
|
|
#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
|
|
#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
|
|
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
|
|
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
|
|
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
|
|
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
|
|
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
|
|
|
|
#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
|
|
#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
|
|
#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
|
|
#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
|
|
#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
|
|
|
|
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
|
|
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
|
|
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
|
|
|
|
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
|
|
#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
|
|
|
|
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
|
|
* rows, which changed the alignment requirements and fence programming.
|
|
*/
|
|
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
|
|
IS_I915GM(dev)))
|
|
#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
|
|
#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
|
|
#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
|
|
#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
|
|
#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
|
|
#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
|
|
/* dsparb controlled by hw only */
|
|
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
|
|
|
|
#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
|
|
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
|
|
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
|
|
#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
|
|
|
|
#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
|
|
#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
|
|
|
|
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
|
|
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
|
|
|
|
#define PRIMARY_RINGBUFFER_SIZE (128*1024)
|
|
|
|
#endif
|