![Yaniv Gardi](/assets/img/avatar_default.png)
Newer revisions of QUALCOMM Technologies UFS host controller may not advertise the correct version information in UFS HCI VER register. To handle this, enable UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION to let UFS standard host controller driver call into vendor specific operation to get right UFS HCI VER register value. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: James Bottomley <JBottomley@Odin.com>
1050 lines
27 KiB
C
1050 lines
27 KiB
C
/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/time.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-qcom-ufs.h>
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#include "ufshcd.h"
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#include "unipro.h"
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#include "ufs-qcom.h"
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#include "ufshci.h"
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static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
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static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result);
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static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
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const char *speed_mode);
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static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote);
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static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
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{
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int err = 0;
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
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if (err)
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dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
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__func__, err);
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return err;
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}
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static int ufs_qcom_host_clk_get(struct device *dev,
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const char *name, struct clk **clk_out)
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{
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struct clk *clk;
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int err = 0;
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clk = devm_clk_get(dev, name);
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if (IS_ERR(clk)) {
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err = PTR_ERR(clk);
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dev_err(dev, "%s: failed to get %s err %d",
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__func__, name, err);
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} else {
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*clk_out = clk;
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}
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return err;
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}
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static int ufs_qcom_host_clk_enable(struct device *dev,
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const char *name, struct clk *clk)
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{
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int err = 0;
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err = clk_prepare_enable(clk);
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if (err)
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dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
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return err;
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}
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static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
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{
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if (!host->is_lane_clks_enabled)
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return;
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clk_disable_unprepare(host->tx_l1_sync_clk);
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clk_disable_unprepare(host->tx_l0_sync_clk);
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clk_disable_unprepare(host->rx_l1_sync_clk);
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clk_disable_unprepare(host->rx_l0_sync_clk);
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host->is_lane_clks_enabled = false;
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}
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static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
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{
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int err = 0;
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struct device *dev = host->hba->dev;
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if (host->is_lane_clks_enabled)
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return 0;
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err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
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host->rx_l0_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
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host->tx_l0_sync_clk);
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if (err)
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goto disable_rx_l0;
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err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
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host->rx_l1_sync_clk);
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if (err)
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goto disable_tx_l0;
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err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
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host->tx_l1_sync_clk);
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if (err)
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goto disable_rx_l1;
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host->is_lane_clks_enabled = true;
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goto out;
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disable_rx_l1:
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clk_disable_unprepare(host->rx_l1_sync_clk);
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disable_tx_l0:
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clk_disable_unprepare(host->tx_l0_sync_clk);
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disable_rx_l0:
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clk_disable_unprepare(host->rx_l0_sync_clk);
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out:
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return err;
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}
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static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
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{
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int err = 0;
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struct device *dev = host->hba->dev;
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err = ufs_qcom_host_clk_get(dev,
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"rx_lane0_sync_clk", &host->rx_l0_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev,
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"tx_lane0_sync_clk", &host->tx_l0_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
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&host->rx_l1_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
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&host->tx_l1_sync_clk);
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out:
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return err;
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}
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static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
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{
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struct ufs_qcom_host *host = hba->priv;
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struct phy *phy = host->generic_phy;
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u32 tx_lanes;
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int err = 0;
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err = ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
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if (err)
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goto out;
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err = ufs_qcom_phy_set_tx_lane_enable(phy, tx_lanes);
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if (err)
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dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable failed\n",
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__func__);
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out:
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return err;
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}
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static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
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{
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int err;
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u32 tx_fsm_val = 0;
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unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
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do {
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
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if (err || tx_fsm_val == TX_FSM_HIBERN8)
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break;
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/* sleep for max. 200us */
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usleep_range(100, 200);
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} while (time_before(jiffies, timeout));
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/*
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* we might have scheduled out for long during polling so
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* check the state again.
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*/
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if (time_after(jiffies, timeout))
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err = ufshcd_dme_get(hba,
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UIC_ARG_MIB(MPHY_TX_FSM_STATE), &tx_fsm_val);
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if (err) {
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dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
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__func__, err);
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} else if (tx_fsm_val != TX_FSM_HIBERN8) {
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err = tx_fsm_val;
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dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
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__func__, err);
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}
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return err;
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}
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static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
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{
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struct ufs_qcom_host *host = hba->priv;
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struct phy *phy = host->generic_phy;
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int ret = 0;
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bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
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? true : false;
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/* Assert PHY reset and apply PHY calibration values */
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ufs_qcom_assert_reset(hba);
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/* provide 1ms delay to let the reset pulse propagate */
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usleep_range(1000, 1100);
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ret = ufs_qcom_phy_calibrate_phy(phy, is_rate_B);
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if (ret) {
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dev_err(hba->dev, "%s: ufs_qcom_phy_calibrate_phy() failed, ret = %d\n",
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__func__, ret);
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goto out;
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}
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/* De-assert PHY reset and start serdes */
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ufs_qcom_deassert_reset(hba);
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/*
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* after reset deassertion, phy will need all ref clocks,
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* voltage, current to settle down before starting serdes.
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*/
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usleep_range(1000, 1100);
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ret = ufs_qcom_phy_start_serdes(phy);
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if (ret) {
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dev_err(hba->dev, "%s: ufs_qcom_phy_start_serdes() failed, ret = %d\n",
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__func__, ret);
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goto out;
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}
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ret = ufs_qcom_phy_is_pcs_ready(phy);
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if (ret)
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dev_err(hba->dev, "%s: is_physical_coding_sublayer_ready() failed, ret = %d\n",
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__func__, ret);
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out:
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return ret;
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}
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/*
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* The UTP controller has a number of internal clock gating cells (CGCs).
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* Internal hardware sub-modules within the UTP controller control the CGCs.
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* Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
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* in a specific operation, UTP controller CGCs are by default disabled and
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* this function enables them (after every UFS link startup) to save some power
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* leakage.
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*/
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static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
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{
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ufshcd_writel(hba,
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ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
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REG_UFS_CFG2);
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/* Ensure that HW clock gating is enabled before next operations */
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mb();
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}
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static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, bool status)
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{
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struct ufs_qcom_host *host = hba->priv;
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int err = 0;
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switch (status) {
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case PRE_CHANGE:
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ufs_qcom_power_up_sequence(hba);
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/*
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* The PHY PLL output is the source of tx/rx lane symbol
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* clocks, hence, enable the lane clocks only after PHY
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* is initialized.
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*/
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err = ufs_qcom_enable_lane_clks(host);
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break;
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case POST_CHANGE:
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/* check if UFS PHY moved from DISABLED to HIBERN8 */
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err = ufs_qcom_check_hibern8(hba);
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ufs_qcom_enable_hw_clk_gating(hba);
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break;
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default:
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dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
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err = -EINVAL;
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break;
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}
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return err;
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}
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/**
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* Returns non-zero for success (which rate of core_clk) and 0
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* in case of a failure
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*/
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static unsigned long
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ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate)
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{
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struct ufs_qcom_host *host = hba->priv;
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struct ufs_clk_info *clki;
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u32 core_clk_period_in_ns;
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u32 tx_clk_cycles_per_us = 0;
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unsigned long core_clk_rate = 0;
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u32 core_clk_cycles_per_us = 0;
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static u32 pwm_fr_table[][2] = {
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{UFS_PWM_G1, 0x1},
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{UFS_PWM_G2, 0x1},
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{UFS_PWM_G3, 0x1},
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{UFS_PWM_G4, 0x1},
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};
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static u32 hs_fr_table_rA[][2] = {
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{UFS_HS_G1, 0x1F},
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{UFS_HS_G2, 0x3e},
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};
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static u32 hs_fr_table_rB[][2] = {
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{UFS_HS_G1, 0x24},
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{UFS_HS_G2, 0x49},
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};
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/*
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* The Qunipro controller does not use following registers:
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* SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
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* UFS_REG_PA_LINK_STARTUP_TIMER
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* But UTP controller uses SYS1CLK_1US_REG register for Interrupt
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* Aggregation logic.
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*/
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if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
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goto out;
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if (gear == 0) {
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dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
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goto out_error;
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}
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list_for_each_entry(clki, &hba->clk_list_head, list) {
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if (!strcmp(clki->name, "core_clk"))
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core_clk_rate = clk_get_rate(clki->clk);
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}
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/* If frequency is smaller than 1MHz, set to 1MHz */
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if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
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core_clk_rate = DEFAULT_CLK_RATE_HZ;
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core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
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ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
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core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
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core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
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core_clk_period_in_ns &= MASK_CLK_NS_REG;
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switch (hs) {
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case FASTAUTO_MODE:
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case FAST_MODE:
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if (rate == PA_HS_MODE_A) {
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if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
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dev_err(hba->dev,
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"%s: index %d exceeds table size %zu\n",
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__func__, gear,
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ARRAY_SIZE(hs_fr_table_rA));
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goto out_error;
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}
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tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
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} else if (rate == PA_HS_MODE_B) {
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if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
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dev_err(hba->dev,
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"%s: index %d exceeds table size %zu\n",
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__func__, gear,
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ARRAY_SIZE(hs_fr_table_rB));
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goto out_error;
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}
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tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
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} else {
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dev_err(hba->dev, "%s: invalid rate = %d\n",
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__func__, rate);
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goto out_error;
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}
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break;
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case SLOWAUTO_MODE:
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case SLOW_MODE:
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if (gear > ARRAY_SIZE(pwm_fr_table)) {
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dev_err(hba->dev,
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"%s: index %d exceeds table size %zu\n",
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__func__, gear,
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ARRAY_SIZE(pwm_fr_table));
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goto out_error;
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}
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tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
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break;
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case UNCHANGED:
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default:
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dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
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goto out_error;
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}
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/* this register 2 fields shall be written at once */
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ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
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REG_UFS_TX_SYMBOL_CLK_NS_US);
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goto out;
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out_error:
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core_clk_rate = 0;
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out:
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return core_clk_rate;
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}
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static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, bool status)
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{
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unsigned long core_clk_rate = 0;
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u32 core_clk_cycles_per_100ms;
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switch (status) {
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case PRE_CHANGE:
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core_clk_rate = ufs_qcom_cfg_timers(hba, UFS_PWM_G1,
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SLOWAUTO_MODE, 0);
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if (!core_clk_rate) {
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dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
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__func__);
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return -EINVAL;
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}
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core_clk_cycles_per_100ms =
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(core_clk_rate / MSEC_PER_SEC) * 100;
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ufshcd_writel(hba, core_clk_cycles_per_100ms,
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REG_UFS_PA_LINK_STARTUP_TIMER);
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break;
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case POST_CHANGE:
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ufs_qcom_link_startup_post_change(hba);
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break;
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default:
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break;
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}
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return 0;
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}
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static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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struct ufs_qcom_host *host = hba->priv;
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struct phy *phy = host->generic_phy;
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int ret = 0;
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if (ufs_qcom_is_link_off(hba)) {
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/*
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* Disable the tx/rx lane symbol clocks before PHY is
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* powered down as the PLL source should be disabled
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* after downstream clocks are disabled.
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*/
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ufs_qcom_disable_lane_clks(host);
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phy_power_off(phy);
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/* Assert PHY soft reset */
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ufs_qcom_assert_reset(hba);
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goto out;
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}
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/*
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* If UniPro link is not active, PHY ref_clk, main PHY analog power
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* rail and low noise analog power rail for PLL can be switched off.
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*/
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if (!ufs_qcom_is_link_active(hba))
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phy_power_off(phy);
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out:
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return ret;
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}
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|
|
static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
struct phy *phy = host->generic_phy;
|
|
int err;
|
|
|
|
err = phy_power_on(phy);
|
|
if (err) {
|
|
dev_err(hba->dev, "%s: failed enabling regs, err = %d\n",
|
|
__func__, err);
|
|
goto out;
|
|
}
|
|
|
|
hba->is_sys_suspended = false;
|
|
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
struct ufs_qcom_dev_params {
|
|
u32 pwm_rx_gear; /* pwm rx gear to work in */
|
|
u32 pwm_tx_gear; /* pwm tx gear to work in */
|
|
u32 hs_rx_gear; /* hs rx gear to work in */
|
|
u32 hs_tx_gear; /* hs tx gear to work in */
|
|
u32 rx_lanes; /* number of rx lanes */
|
|
u32 tx_lanes; /* number of tx lanes */
|
|
u32 rx_pwr_pwm; /* rx pwm working pwr */
|
|
u32 tx_pwr_pwm; /* tx pwm working pwr */
|
|
u32 rx_pwr_hs; /* rx hs working pwr */
|
|
u32 tx_pwr_hs; /* tx hs working pwr */
|
|
u32 hs_rate; /* rate A/B to work in HS */
|
|
u32 desired_working_mode;
|
|
};
|
|
|
|
static int ufs_qcom_get_pwr_dev_param(struct ufs_qcom_dev_params *qcom_param,
|
|
struct ufs_pa_layer_attr *dev_max,
|
|
struct ufs_pa_layer_attr *agreed_pwr)
|
|
{
|
|
int min_qcom_gear;
|
|
int min_dev_gear;
|
|
bool is_dev_sup_hs = false;
|
|
bool is_qcom_max_hs = false;
|
|
|
|
if (dev_max->pwr_rx == FAST_MODE)
|
|
is_dev_sup_hs = true;
|
|
|
|
if (qcom_param->desired_working_mode == FAST) {
|
|
is_qcom_max_hs = true;
|
|
min_qcom_gear = min_t(u32, qcom_param->hs_rx_gear,
|
|
qcom_param->hs_tx_gear);
|
|
} else {
|
|
min_qcom_gear = min_t(u32, qcom_param->pwm_rx_gear,
|
|
qcom_param->pwm_tx_gear);
|
|
}
|
|
|
|
/*
|
|
* device doesn't support HS but qcom_param->desired_working_mode is
|
|
* HS, thus device and qcom_param don't agree
|
|
*/
|
|
if (!is_dev_sup_hs && is_qcom_max_hs) {
|
|
pr_err("%s: failed to agree on power mode (device doesn't support HS but requested power is HS)\n",
|
|
__func__);
|
|
return -ENOTSUPP;
|
|
} else if (is_dev_sup_hs && is_qcom_max_hs) {
|
|
/*
|
|
* since device supports HS, it supports FAST_MODE.
|
|
* since qcom_param->desired_working_mode is also HS
|
|
* then final decision (FAST/FASTAUTO) is done according
|
|
* to qcom_params as it is the restricting factor
|
|
*/
|
|
agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
|
|
qcom_param->rx_pwr_hs;
|
|
} else {
|
|
/*
|
|
* here qcom_param->desired_working_mode is PWM.
|
|
* it doesn't matter whether device supports HS or PWM,
|
|
* in both cases qcom_param->desired_working_mode will
|
|
* determine the mode
|
|
*/
|
|
agreed_pwr->pwr_rx = agreed_pwr->pwr_tx =
|
|
qcom_param->rx_pwr_pwm;
|
|
}
|
|
|
|
/*
|
|
* we would like tx to work in the minimum number of lanes
|
|
* between device capability and vendor preferences.
|
|
* the same decision will be made for rx
|
|
*/
|
|
agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
|
|
qcom_param->tx_lanes);
|
|
agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
|
|
qcom_param->rx_lanes);
|
|
|
|
/* device maximum gear is the minimum between device rx and tx gears */
|
|
min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
|
|
|
|
/*
|
|
* if both device capabilities and vendor pre-defined preferences are
|
|
* both HS or both PWM then set the minimum gear to be the chosen
|
|
* working gear.
|
|
* if one is PWM and one is HS then the one that is PWM get to decide
|
|
* what is the gear, as it is the one that also decided previously what
|
|
* pwr the device will be configured to.
|
|
*/
|
|
if ((is_dev_sup_hs && is_qcom_max_hs) ||
|
|
(!is_dev_sup_hs && !is_qcom_max_hs))
|
|
agreed_pwr->gear_rx = agreed_pwr->gear_tx =
|
|
min_t(u32, min_dev_gear, min_qcom_gear);
|
|
else if (!is_dev_sup_hs)
|
|
agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_dev_gear;
|
|
else
|
|
agreed_pwr->gear_rx = agreed_pwr->gear_tx = min_qcom_gear;
|
|
|
|
agreed_pwr->hs_rate = qcom_param->hs_rate;
|
|
return 0;
|
|
}
|
|
|
|
static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
|
|
{
|
|
int vote;
|
|
int err = 0;
|
|
char mode[BUS_VECTOR_NAME_LEN];
|
|
|
|
ufs_qcom_get_speed_mode(&host->dev_req_params, mode);
|
|
|
|
vote = ufs_qcom_get_bus_vote(host, mode);
|
|
if (vote >= 0)
|
|
err = ufs_qcom_set_bus_vote(host, vote);
|
|
else
|
|
err = vote;
|
|
|
|
if (err)
|
|
dev_err(host->hba->dev, "%s: failed %d\n", __func__, err);
|
|
else
|
|
host->bus_vote.saved_vote = vote;
|
|
return err;
|
|
}
|
|
|
|
static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
|
|
bool status,
|
|
struct ufs_pa_layer_attr *dev_max_params,
|
|
struct ufs_pa_layer_attr *dev_req_params)
|
|
{
|
|
u32 val;
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
struct phy *phy = host->generic_phy;
|
|
struct ufs_qcom_dev_params ufs_qcom_cap;
|
|
int ret = 0;
|
|
int res = 0;
|
|
|
|
if (!dev_req_params) {
|
|
pr_err("%s: incoming dev_req_params is NULL\n", __func__);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
switch (status) {
|
|
case PRE_CHANGE:
|
|
ufs_qcom_cap.tx_lanes = UFS_QCOM_LIMIT_NUM_LANES_TX;
|
|
ufs_qcom_cap.rx_lanes = UFS_QCOM_LIMIT_NUM_LANES_RX;
|
|
ufs_qcom_cap.hs_rx_gear = UFS_QCOM_LIMIT_HSGEAR_RX;
|
|
ufs_qcom_cap.hs_tx_gear = UFS_QCOM_LIMIT_HSGEAR_TX;
|
|
ufs_qcom_cap.pwm_rx_gear = UFS_QCOM_LIMIT_PWMGEAR_RX;
|
|
ufs_qcom_cap.pwm_tx_gear = UFS_QCOM_LIMIT_PWMGEAR_TX;
|
|
ufs_qcom_cap.rx_pwr_pwm = UFS_QCOM_LIMIT_RX_PWR_PWM;
|
|
ufs_qcom_cap.tx_pwr_pwm = UFS_QCOM_LIMIT_TX_PWR_PWM;
|
|
ufs_qcom_cap.rx_pwr_hs = UFS_QCOM_LIMIT_RX_PWR_HS;
|
|
ufs_qcom_cap.tx_pwr_hs = UFS_QCOM_LIMIT_TX_PWR_HS;
|
|
ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
|
|
ufs_qcom_cap.desired_working_mode =
|
|
UFS_QCOM_LIMIT_DESIRED_MODE;
|
|
|
|
ret = ufs_qcom_get_pwr_dev_param(&ufs_qcom_cap,
|
|
dev_max_params,
|
|
dev_req_params);
|
|
if (ret) {
|
|
pr_err("%s: failed to determine capabilities\n",
|
|
__func__);
|
|
goto out;
|
|
}
|
|
|
|
break;
|
|
case POST_CHANGE:
|
|
if (!ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
|
|
dev_req_params->pwr_rx,
|
|
dev_req_params->hs_rate)) {
|
|
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
|
|
__func__);
|
|
/*
|
|
* we return error code at the end of the routine,
|
|
* but continue to configure UFS_PHY_TX_LANE_ENABLE
|
|
* and bus voting as usual
|
|
*/
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
val = ~(MAX_U32 << dev_req_params->lane_tx);
|
|
res = ufs_qcom_phy_set_tx_lane_enable(phy, val);
|
|
if (res) {
|
|
dev_err(hba->dev, "%s: ufs_qcom_phy_set_tx_lane_enable() failed res = %d\n",
|
|
__func__, res);
|
|
ret = res;
|
|
}
|
|
|
|
/* cache the power mode parameters to use internally */
|
|
memcpy(&host->dev_req_params,
|
|
dev_req_params, sizeof(*dev_req_params));
|
|
ufs_qcom_update_bus_bw_vote(host);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
|
|
if (host->hw_ver.major == 0x1)
|
|
return UFSHCI_VERSION_11;
|
|
else
|
|
return UFSHCI_VERSION_20;
|
|
}
|
|
|
|
/**
|
|
* ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
|
|
* @hba: host controller instance
|
|
*
|
|
* QCOM UFS host controller might have some non standard behaviours (quirks)
|
|
* than what is specified by UFSHCI specification. Advertise all such
|
|
* quirks to standard UFS host controller driver so standard takes them into
|
|
* account.
|
|
*/
|
|
static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
|
|
if (host->hw_ver.major == 0x01) {
|
|
hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
|
|
| UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
|
|
| UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
|
|
|
|
if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
|
|
hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
|
|
}
|
|
|
|
if (host->hw_ver.major >= 0x2) {
|
|
hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
|
|
hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
|
|
|
|
if (!ufs_qcom_cap_qunipro(host))
|
|
/* Legacy UniPro mode still need following quirks */
|
|
hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
|
|
| UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
|
|
| UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
|
|
}
|
|
}
|
|
|
|
static void ufs_qcom_set_caps(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
|
|
if (host->hw_ver.major >= 0x2)
|
|
host->caps = UFS_QCOM_CAP_QUNIPRO;
|
|
}
|
|
|
|
static int ufs_qcom_get_bus_vote(struct ufs_qcom_host *host,
|
|
const char *speed_mode)
|
|
{
|
|
struct device *dev = host->hba->dev;
|
|
struct device_node *np = dev->of_node;
|
|
int err;
|
|
const char *key = "qcom,bus-vector-names";
|
|
|
|
if (!speed_mode) {
|
|
err = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
if (host->bus_vote.is_max_bw_needed && !!strcmp(speed_mode, "MIN"))
|
|
err = of_property_match_string(np, key, "MAX");
|
|
else
|
|
err = of_property_match_string(np, key, speed_mode);
|
|
|
|
out:
|
|
if (err < 0)
|
|
dev_err(dev, "%s: Invalid %s mode %d\n",
|
|
__func__, speed_mode, err);
|
|
return err;
|
|
}
|
|
|
|
static int ufs_qcom_set_bus_vote(struct ufs_qcom_host *host, int vote)
|
|
{
|
|
int err = 0;
|
|
|
|
if (vote != host->bus_vote.curr_vote)
|
|
host->bus_vote.curr_vote = vote;
|
|
|
|
return err;
|
|
}
|
|
|
|
static void ufs_qcom_get_speed_mode(struct ufs_pa_layer_attr *p, char *result)
|
|
{
|
|
int gear = max_t(u32, p->gear_rx, p->gear_tx);
|
|
int lanes = max_t(u32, p->lane_rx, p->lane_tx);
|
|
int pwr;
|
|
|
|
/* default to PWM Gear 1, Lane 1 if power mode is not initialized */
|
|
if (!gear)
|
|
gear = 1;
|
|
|
|
if (!lanes)
|
|
lanes = 1;
|
|
|
|
if (!p->pwr_rx && !p->pwr_tx) {
|
|
pwr = SLOWAUTO_MODE;
|
|
snprintf(result, BUS_VECTOR_NAME_LEN, "MIN");
|
|
} else if (p->pwr_rx == FAST_MODE || p->pwr_rx == FASTAUTO_MODE ||
|
|
p->pwr_tx == FAST_MODE || p->pwr_tx == FASTAUTO_MODE) {
|
|
pwr = FAST_MODE;
|
|
snprintf(result, BUS_VECTOR_NAME_LEN, "%s_R%s_G%d_L%d", "HS",
|
|
p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes);
|
|
} else {
|
|
pwr = SLOW_MODE;
|
|
snprintf(result, BUS_VECTOR_NAME_LEN, "%s_G%d_L%d",
|
|
"PWM", gear, lanes);
|
|
}
|
|
}
|
|
|
|
static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
int err = 0;
|
|
int vote = 0;
|
|
|
|
/*
|
|
* In case ufs_qcom_init() is not yet done, simply ignore.
|
|
* This ufs_qcom_setup_clocks() shall be called from
|
|
* ufs_qcom_init() after init is done.
|
|
*/
|
|
if (!host)
|
|
return 0;
|
|
|
|
if (on) {
|
|
err = ufs_qcom_phy_enable_iface_clk(host->generic_phy);
|
|
if (err)
|
|
goto out;
|
|
|
|
err = ufs_qcom_phy_enable_ref_clk(host->generic_phy);
|
|
if (err) {
|
|
dev_err(hba->dev, "%s enable phy ref clock failed, err=%d\n",
|
|
__func__, err);
|
|
ufs_qcom_phy_disable_iface_clk(host->generic_phy);
|
|
goto out;
|
|
}
|
|
/* enable the device ref clock */
|
|
ufs_qcom_phy_enable_dev_ref_clk(host->generic_phy);
|
|
vote = host->bus_vote.saved_vote;
|
|
if (vote == host->bus_vote.min_bw_vote)
|
|
ufs_qcom_update_bus_bw_vote(host);
|
|
} else {
|
|
/* M-PHY RMMI interface clocks can be turned off */
|
|
ufs_qcom_phy_disable_iface_clk(host->generic_phy);
|
|
if (!ufs_qcom_is_link_active(hba)) {
|
|
/* turn off UFS local PHY ref_clk */
|
|
ufs_qcom_phy_disable_ref_clk(host->generic_phy);
|
|
/* disable device ref_clk */
|
|
ufs_qcom_phy_disable_dev_ref_clk(host->generic_phy);
|
|
}
|
|
vote = host->bus_vote.min_bw_vote;
|
|
}
|
|
|
|
err = ufs_qcom_set_bus_vote(host, vote);
|
|
if (err)
|
|
dev_err(hba->dev, "%s: set bus vote failed %d\n",
|
|
__func__, err);
|
|
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
static ssize_t
|
|
show_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%u\n",
|
|
host->bus_vote.is_max_bw_needed);
|
|
}
|
|
|
|
static ssize_t
|
|
store_ufs_to_mem_max_bus_bw(struct device *dev, struct device_attribute *attr,
|
|
const char *buf, size_t count)
|
|
{
|
|
struct ufs_hba *hba = dev_get_drvdata(dev);
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
uint32_t value;
|
|
|
|
if (!kstrtou32(buf, 0, &value)) {
|
|
host->bus_vote.is_max_bw_needed = !!value;
|
|
ufs_qcom_update_bus_bw_vote(host);
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
static int ufs_qcom_bus_register(struct ufs_qcom_host *host)
|
|
{
|
|
int err;
|
|
struct device *dev = host->hba->dev;
|
|
struct device_node *np = dev->of_node;
|
|
|
|
err = of_property_count_strings(np, "qcom,bus-vector-names");
|
|
if (err < 0 ) {
|
|
dev_err(dev, "%s: qcom,bus-vector-names not specified correctly %d\n",
|
|
__func__, err);
|
|
goto out;
|
|
}
|
|
|
|
/* cache the vote index for minimum and maximum bandwidth */
|
|
host->bus_vote.min_bw_vote = ufs_qcom_get_bus_vote(host, "MIN");
|
|
host->bus_vote.max_bw_vote = ufs_qcom_get_bus_vote(host, "MAX");
|
|
|
|
host->bus_vote.max_bus_bw.show = show_ufs_to_mem_max_bus_bw;
|
|
host->bus_vote.max_bus_bw.store = store_ufs_to_mem_max_bus_bw;
|
|
sysfs_attr_init(&host->bus_vote.max_bus_bw.attr);
|
|
host->bus_vote.max_bus_bw.attr.name = "max_bus_bw";
|
|
host->bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR;
|
|
err = device_create_file(dev, &host->bus_vote.max_bus_bw);
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
#define ANDROID_BOOT_DEV_MAX 30
|
|
static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
|
|
static int get_android_boot_dev(char *str)
|
|
{
|
|
strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
|
|
return 1;
|
|
}
|
|
__setup("androidboot.bootdevice=", get_android_boot_dev);
|
|
|
|
/**
|
|
* ufs_qcom_init - bind phy with controller
|
|
* @hba: host controller instance
|
|
*
|
|
* Binds PHY with controller and powers up PHY enabling clocks
|
|
* and regulators.
|
|
*
|
|
* Returns -EPROBE_DEFER if binding fails, returns negative error
|
|
* on phy power up failure and returns zero on success.
|
|
*/
|
|
static int ufs_qcom_init(struct ufs_hba *hba)
|
|
{
|
|
int err;
|
|
struct device *dev = hba->dev;
|
|
struct ufs_qcom_host *host;
|
|
|
|
if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
|
|
return -ENODEV;
|
|
|
|
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
|
|
if (!host) {
|
|
err = -ENOMEM;
|
|
dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
|
|
goto out;
|
|
}
|
|
|
|
host->hba = hba;
|
|
hba->priv = (void *)host;
|
|
|
|
host->generic_phy = devm_phy_get(dev, "ufsphy");
|
|
|
|
if (IS_ERR(host->generic_phy)) {
|
|
err = PTR_ERR(host->generic_phy);
|
|
dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
|
|
goto out;
|
|
}
|
|
|
|
err = ufs_qcom_bus_register(host);
|
|
if (err)
|
|
goto out_host_free;
|
|
|
|
ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
|
|
&host->hw_ver.minor, &host->hw_ver.step);
|
|
|
|
/* update phy revision information before calling phy_init() */
|
|
ufs_qcom_phy_save_controller_version(host->generic_phy,
|
|
host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
|
|
|
|
phy_init(host->generic_phy);
|
|
err = phy_power_on(host->generic_phy);
|
|
if (err)
|
|
goto out_unregister_bus;
|
|
|
|
err = ufs_qcom_init_lane_clks(host);
|
|
if (err)
|
|
goto out_disable_phy;
|
|
|
|
ufs_qcom_set_caps(hba);
|
|
ufs_qcom_advertise_quirks(hba);
|
|
|
|
hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_CLK_SCALING;
|
|
hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
|
|
|
|
ufs_qcom_setup_clocks(hba, true);
|
|
|
|
if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
|
|
ufs_qcom_hosts[hba->dev->id] = host;
|
|
|
|
goto out;
|
|
|
|
out_disable_phy:
|
|
phy_power_off(host->generic_phy);
|
|
out_unregister_bus:
|
|
phy_exit(host->generic_phy);
|
|
out_host_free:
|
|
devm_kfree(dev, host);
|
|
hba->priv = NULL;
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
static void ufs_qcom_exit(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
|
|
ufs_qcom_disable_lane_clks(host);
|
|
phy_power_off(host->generic_phy);
|
|
}
|
|
|
|
static
|
|
void ufs_qcom_clk_scale_notify(struct ufs_hba *hba)
|
|
{
|
|
struct ufs_qcom_host *host = hba->priv;
|
|
struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
|
|
|
|
if (!dev_req_params)
|
|
return;
|
|
|
|
ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
|
|
dev_req_params->pwr_rx,
|
|
dev_req_params->hs_rate);
|
|
}
|
|
|
|
/**
|
|
* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
|
|
*
|
|
* The variant operations configure the necessary controller and PHY
|
|
* handshake during initialization.
|
|
*/
|
|
static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
|
|
.name = "qcom",
|
|
.init = ufs_qcom_init,
|
|
.exit = ufs_qcom_exit,
|
|
.get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
|
|
.clk_scale_notify = ufs_qcom_clk_scale_notify,
|
|
.setup_clocks = ufs_qcom_setup_clocks,
|
|
.hce_enable_notify = ufs_qcom_hce_enable_notify,
|
|
.link_startup_notify = ufs_qcom_link_startup_notify,
|
|
.pwr_change_notify = ufs_qcom_pwr_change_notify,
|
|
.suspend = ufs_qcom_suspend,
|
|
.resume = ufs_qcom_resume,
|
|
};
|
|
EXPORT_SYMBOL(ufs_hba_qcom_vops);
|