![Harvey Harrison](/assets/img/avatar_default.png)
__FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* xilinx_spi.c
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*
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* Xilinx SPI controller driver (master mode only)
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2002-2007 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is licensed
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* "as is" without any warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/io.h>
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#include <syslib/virtex_devices.h>
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#define XILINX_SPI_NAME "xilinx_spi"
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/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
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* Product Specification", DS464
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*/
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#define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */
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#define XSPI_CR_ENABLE 0x02
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#define XSPI_CR_MASTER_MODE 0x04
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#define XSPI_CR_CPOL 0x08
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#define XSPI_CR_CPHA 0x10
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#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
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#define XSPI_CR_TXFIFO_RESET 0x20
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#define XSPI_CR_RXFIFO_RESET 0x40
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#define XSPI_CR_MANUAL_SSELECT 0x80
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#define XSPI_CR_TRANS_INHIBIT 0x100
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#define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */
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#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
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#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
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#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
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#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
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#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
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#define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */
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#define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */
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#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
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/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
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* IPIF registers are 32 bit
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*/
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#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
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#define XIPIF_V123B_GINTR_ENABLE 0x80000000
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#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
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#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
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#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
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#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
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* disabled */
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#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
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#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
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#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
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#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
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#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
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#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
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struct xilinx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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void __iomem *regs; /* virt. address of the control registers */
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u32 irq;
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u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
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u8 *rx_ptr; /* pointer in the Tx buffer */
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const u8 *tx_ptr; /* pointer in the Rx buffer */
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int remaining_bytes; /* the number of bytes left to transfer */
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};
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static void xspi_init_hw(void __iomem *regs_base)
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{
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/* Reset the SPI device */
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out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET,
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XIPIF_V123B_RESET_MASK);
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/* Disable all the interrupts just in case */
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out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0);
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/* Enable the global IPIF interrupt */
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out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET,
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XIPIF_V123B_GINTR_ENABLE);
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/* Deselect the slave on the SPI bus */
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out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff);
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/* Disable the transmitter, enable Manual Slave Select Assertion,
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* put SPI controller into master mode, and enable it */
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out_be16(regs_base + XSPI_CR_OFFSET,
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XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT
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| XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE);
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}
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static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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if (is_on == BITBANG_CS_INACTIVE) {
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/* Deselect the slave on the SPI bus */
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out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff);
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} else if (is_on == BITBANG_CS_ACTIVE) {
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/* Set the SPI clock phase and polarity */
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u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET)
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& ~XSPI_CR_MODE_MASK;
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if (spi->mode & SPI_CPHA)
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cr |= XSPI_CR_CPHA;
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if (spi->mode & SPI_CPOL)
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cr |= XSPI_CR_CPOL;
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out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
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/* We do not check spi->max_speed_hz here as the SPI clock
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* frequency is not software programmable (the IP block design
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* parameter)
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*/
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/* Activate the chip select */
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out_be32(xspi->regs + XSPI_SSR_OFFSET,
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~(0x0001 << spi->chip_select));
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}
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}
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/* spi_bitbang requires custom setup_transfer() to be defined if there is a
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* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
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* supports just 8 bits per word, and SPI clock can't be changed in software.
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* Check for 8 bits per word. Chip select delay calculations could be
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* added here as soon as bitbang_work() can be made aware of the delay value.
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*/
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static int xilinx_spi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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u8 bits_per_word;
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u32 hz;
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
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hz = (t) ? t->speed_hz : spi->max_speed_hz;
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if (bits_per_word != 8) {
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dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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__func__, bits_per_word);
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return -EINVAL;
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}
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if (hz && xspi->speed_hz > hz) {
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dev_err(&spi->dev, "%s, unsupported clock rate %uHz\n",
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__func__, hz);
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return -EINVAL;
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}
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return 0;
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CPOL | SPI_CPHA)
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static int xilinx_spi_setup(struct spi_device *spi)
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{
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struct spi_bitbang *bitbang;
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struct xilinx_spi *xspi;
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int retval;
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xspi = spi_master_get_devdata(spi->master);
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bitbang = &xspi->bitbang;
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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if (spi->mode & ~MODEBITS) {
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dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
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__func__, spi->mode & ~MODEBITS);
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return -EINVAL;
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}
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retval = xilinx_spi_setup_transfer(spi, NULL);
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if (retval < 0)
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return retval;
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dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
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__func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
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return 0;
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}
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static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
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{
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u8 sr;
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/* Fill the Tx FIFO with as many bytes as possible */
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sr = in_8(xspi->regs + XSPI_SR_OFFSET);
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while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
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if (xspi->tx_ptr) {
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out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++);
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} else {
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out_8(xspi->regs + XSPI_TXD_OFFSET, 0);
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}
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xspi->remaining_bytes--;
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sr = in_8(xspi->regs + XSPI_SR_OFFSET);
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}
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}
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static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
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{
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struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
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u32 ipif_ier;
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u16 cr;
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/* We get here with transmitter inhibited */
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xspi->tx_ptr = t->tx_buf;
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xspi->rx_ptr = t->rx_buf;
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xspi->remaining_bytes = t->len;
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INIT_COMPLETION(xspi->done);
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xilinx_spi_fill_tx_fifo(xspi);
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/* Enable the transmit empty interrupt, which we use to determine
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* progress on the transmission.
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*/
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ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET);
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out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET,
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ipif_ier | XSPI_INTR_TX_EMPTY);
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/* Start the transfer by not inhibiting the transmitter any longer */
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cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT;
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out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
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wait_for_completion(&xspi->done);
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/* Disable the transmit empty interrupt */
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out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier);
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return t->len - xspi->remaining_bytes;
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}
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/* This driver supports single master mode only. Hence Tx FIFO Empty
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* is the only interrupt we care about.
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* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
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* Fault are not to happen.
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*/
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static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
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{
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struct xilinx_spi *xspi = dev_id;
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u32 ipif_isr;
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/* Get the IPIF interrupts, and clear them immediately */
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ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET);
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out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr);
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if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
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u16 cr;
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u8 sr;
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/* A transmit has just completed. Process received data and
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* check for more data to transmit. Always inhibit the
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* transmitter while the Isr refills the transmit register/FIFO,
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* or make sure it is stopped if we're done.
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*/
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cr = in_be16(xspi->regs + XSPI_CR_OFFSET);
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out_be16(xspi->regs + XSPI_CR_OFFSET,
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cr | XSPI_CR_TRANS_INHIBIT);
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/* Read out all the data from the Rx FIFO */
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sr = in_8(xspi->regs + XSPI_SR_OFFSET);
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while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
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u8 data;
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data = in_8(xspi->regs + XSPI_RXD_OFFSET);
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if (xspi->rx_ptr) {
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*xspi->rx_ptr++ = data;
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}
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sr = in_8(xspi->regs + XSPI_SR_OFFSET);
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}
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/* See if there is more data to send */
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if (xspi->remaining_bytes > 0) {
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xilinx_spi_fill_tx_fifo(xspi);
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/* Start the transfer by not inhibiting the
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* transmitter any longer
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*/
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out_be16(xspi->regs + XSPI_CR_OFFSET, cr);
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} else {
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/* No more data to send.
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* Indicate the transfer is completed.
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*/
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complete(&xspi->done);
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}
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}
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return IRQ_HANDLED;
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}
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static int __init xilinx_spi_probe(struct platform_device *dev)
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{
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int ret = 0;
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struct spi_master *master;
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struct xilinx_spi *xspi;
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struct xspi_platform_data *pdata;
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struct resource *r;
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/* Get resources(memory, IRQ) associated with the device */
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master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));
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if (master == NULL) {
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return -ENOMEM;
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}
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platform_set_drvdata(dev, master);
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pdata = dev->dev.platform_data;
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if (pdata == NULL) {
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ret = -ENODEV;
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goto put_master;
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}
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r = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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ret = -ENODEV;
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goto put_master;
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}
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xspi = spi_master_get_devdata(master);
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xspi->bitbang.master = spi_master_get(master);
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xspi->bitbang.chipselect = xilinx_spi_chipselect;
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xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
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xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
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xspi->bitbang.master->setup = xilinx_spi_setup;
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init_completion(&xspi->done);
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if (!request_mem_region(r->start,
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r->end - r->start + 1, XILINX_SPI_NAME)) {
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ret = -ENXIO;
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goto put_master;
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}
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xspi->regs = ioremap(r->start, r->end - r->start + 1);
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if (xspi->regs == NULL) {
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ret = -ENOMEM;
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goto put_master;
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}
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xspi->irq = platform_get_irq(dev, 0);
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if (xspi->irq < 0) {
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ret = -ENXIO;
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goto unmap_io;
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}
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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xspi->speed_hz = pdata->speed_hz;
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/* SPI controller initializations */
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xspi_init_hw(xspi->regs);
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/* Register for SPI Interrupt */
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ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
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if (ret != 0)
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goto unmap_io;
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ret = spi_bitbang_start(&xspi->bitbang);
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if (ret != 0) {
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dev_err(&dev->dev, "spi_bitbang_start FAILED\n");
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goto free_irq;
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}
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dev_info(&dev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n",
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r->start, (u32)xspi->regs, xspi->irq);
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return ret;
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free_irq:
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free_irq(xspi->irq, xspi);
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unmap_io:
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iounmap(xspi->regs);
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put_master:
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spi_master_put(master);
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return ret;
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}
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static int __devexit xilinx_spi_remove(struct platform_device *dev)
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{
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struct xilinx_spi *xspi;
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struct spi_master *master;
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master = platform_get_drvdata(dev);
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xspi = spi_master_get_devdata(master);
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spi_bitbang_stop(&xspi->bitbang);
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free_irq(xspi->irq, xspi);
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iounmap(xspi->regs);
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platform_set_drvdata(dev, 0);
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spi_master_put(xspi->bitbang.master);
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return 0;
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("platform:" XILINX_SPI_NAME);
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static struct platform_driver xilinx_spi_driver = {
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.probe = xilinx_spi_probe,
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.remove = __devexit_p(xilinx_spi_remove),
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.driver = {
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.name = XILINX_SPI_NAME,
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.owner = THIS_MODULE,
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},
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};
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static int __init xilinx_spi_init(void)
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{
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return platform_driver_register(&xilinx_spi_driver);
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}
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module_init(xilinx_spi_init);
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static void __exit xilinx_spi_exit(void)
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{
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platform_driver_unregister(&xilinx_spi_driver);
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}
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module_exit(xilinx_spi_exit);
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MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
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MODULE_DESCRIPTION("Xilinx SPI driver");
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MODULE_LICENSE("GPL");
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