821 lines
20 KiB
C
821 lines
20 KiB
C
/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/device.h>
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#include <linux/netdevice.h>
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#include "en.h"
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#define MLX5E_MAX_PRIORITY 8
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#define MLX5E_100MB (100000)
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#define MLX5E_1GB (1000000)
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#define MLX5E_CEE_STATE_UP 1
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#define MLX5E_CEE_STATE_DOWN 0
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enum {
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MLX5E_VENDOR_TC_GROUP_NUM = 7,
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MLX5E_LOWEST_PRIO_GROUP = 0,
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};
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/* If dcbx mode is non-host set the dcbx mode to host.
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*/
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static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
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enum mlx5_dcbx_oper_mode mode)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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u32 param[MLX5_ST_SZ_DW(dcbx_param)];
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int err;
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err = mlx5_query_port_dcbx_param(mdev, param);
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if (err)
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return err;
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MLX5_SET(dcbx_param, param, version_admin, mode);
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if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
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MLX5_SET(dcbx_param, param, willing_admin, 1);
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return mlx5_set_port_dcbx_param(mdev, param);
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}
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static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
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{
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struct mlx5e_dcbx *dcbx = &priv->dcbx;
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int err;
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if (!MLX5_CAP_GEN(priv->mdev, dcbx))
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return 0;
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if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
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return 0;
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err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
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if (err)
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return err;
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dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
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return 0;
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}
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static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
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struct ieee_ets *ets)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 tc_group[IEEE_8021QAZ_MAX_TCS];
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bool is_tc_group_6_exist = false;
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bool is_zero_bw_ets_tc = false;
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int err = 0;
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int i;
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if (!MLX5_CAP_GEN(priv->mdev, ets))
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return -EOPNOTSUPP;
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ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
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for (i = 0; i < ets->ets_cap; i++) {
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err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
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if (err)
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return err;
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err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]);
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if (err)
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return err;
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err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
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if (err)
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return err;
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if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC &&
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tc_group[i] == (MLX5E_LOWEST_PRIO_GROUP + 1))
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is_zero_bw_ets_tc = true;
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if (tc_group[i] == (MLX5E_VENDOR_TC_GROUP_NUM - 1))
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is_tc_group_6_exist = true;
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}
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/* Report 0% ets tc if exits*/
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if (is_zero_bw_ets_tc) {
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for (i = 0; i < ets->ets_cap; i++)
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if (tc_group[i] == MLX5E_LOWEST_PRIO_GROUP)
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ets->tc_tx_bw[i] = 0;
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}
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/* Update tc_tsa based on fw setting*/
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for (i = 0; i < ets->ets_cap; i++) {
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if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
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priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
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else if (tc_group[i] == MLX5E_VENDOR_TC_GROUP_NUM &&
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!is_tc_group_6_exist)
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priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
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}
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memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
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return err;
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}
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static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
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{
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bool any_tc_mapped_to_ets = false;
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bool ets_zero_bw = false;
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int strict_group;
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int i;
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for (i = 0; i <= max_tc; i++) {
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if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
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any_tc_mapped_to_ets = true;
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if (!ets->tc_tx_bw[i])
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ets_zero_bw = true;
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}
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}
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/* strict group has higher priority than ets group */
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strict_group = MLX5E_LOWEST_PRIO_GROUP;
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if (any_tc_mapped_to_ets)
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strict_group++;
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if (ets_zero_bw)
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strict_group++;
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for (i = 0; i <= max_tc; i++) {
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_VENDOR:
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tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
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break;
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case IEEE_8021QAZ_TSA_STRICT:
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tc_group[i] = strict_group++;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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tc_group[i] = MLX5E_LOWEST_PRIO_GROUP;
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if (ets->tc_tx_bw[i] && ets_zero_bw)
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tc_group[i] = MLX5E_LOWEST_PRIO_GROUP + 1;
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break;
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}
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}
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}
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static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
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u8 *tc_group, int max_tc)
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{
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int bw_for_ets_zero_bw_tc = 0;
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int last_ets_zero_bw_tc = -1;
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int num_ets_zero_bw = 0;
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int i;
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for (i = 0; i <= max_tc; i++) {
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if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS &&
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!ets->tc_tx_bw[i]) {
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num_ets_zero_bw++;
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last_ets_zero_bw_tc = i;
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}
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}
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if (num_ets_zero_bw)
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bw_for_ets_zero_bw_tc = MLX5E_MAX_BW_ALLOC / num_ets_zero_bw;
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for (i = 0; i <= max_tc; i++) {
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_VENDOR:
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tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
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break;
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case IEEE_8021QAZ_TSA_STRICT:
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tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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tc_tx_bw[i] = ets->tc_tx_bw[i] ?
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ets->tc_tx_bw[i] :
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bw_for_ets_zero_bw_tc;
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break;
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}
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}
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/* Make sure the total bw for ets zero bw group is 100% */
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if (last_ets_zero_bw_tc != -1)
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tc_tx_bw[last_ets_zero_bw_tc] +=
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MLX5E_MAX_BW_ALLOC % num_ets_zero_bw;
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}
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/* If there are ETS BW 0,
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* Set ETS group # to 1 for all ETS non zero BW tcs. Their sum must be 100%.
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* Set group #0 to all the ETS BW 0 tcs and
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* equally splits the 100% BW between them
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* Report both group #0 and #1 as ETS type.
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* All the tcs in group #0 will be reported with 0% BW.
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*/
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int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
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u8 tc_group[IEEE_8021QAZ_MAX_TCS];
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int max_tc = mlx5_max_tc(mdev);
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int err;
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mlx5e_build_tc_group(ets, tc_group, max_tc);
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mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
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err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
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if (err)
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return err;
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err = mlx5_set_port_tc_group(mdev, tc_group);
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if (err)
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return err;
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err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
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if (err)
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return err;
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memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
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return err;
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}
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static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
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struct ieee_ets *ets)
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{
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int bw_sum = 0;
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int i;
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/* Validate Priority */
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
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netdev_err(netdev,
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"Failed to validate ETS: priority value greater than max(%d)\n",
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MLX5E_MAX_PRIORITY);
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return -EINVAL;
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}
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}
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/* Validate Bandwidth Sum */
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
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if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
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bw_sum += ets->tc_tx_bw[i];
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if (bw_sum != 0 && bw_sum != 100) {
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netdev_err(netdev,
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"Failed to validate ETS: BW sum is illegal\n");
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return -EINVAL;
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}
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return 0;
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}
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static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
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struct ieee_ets *ets)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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int err;
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if (!MLX5_CAP_GEN(priv->mdev, ets))
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return -EOPNOTSUPP;
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err = mlx5e_dbcnl_validate_ets(netdev, ets);
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if (err)
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return err;
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err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
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if (err)
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return err;
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return 0;
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}
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static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
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struct ieee_pfc *pfc)
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{
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struct mlx5e_priv *priv = netdev_priv(dev);
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5e_pport_stats *pstats = &priv->stats.pport;
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int i;
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pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
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pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
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}
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return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
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}
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static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
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struct ieee_pfc *pfc)
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{
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struct mlx5e_priv *priv = netdev_priv(dev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 curr_pfc_en;
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int ret;
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mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
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if (pfc->pfc_en == curr_pfc_en)
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return 0;
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ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
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mlx5_toggle_port_link(mdev);
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return ret;
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}
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static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
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{
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struct mlx5e_priv *priv = netdev_priv(dev);
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return priv->dcbx.cap;
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}
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static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
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{
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struct mlx5e_priv *priv = netdev_priv(dev);
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struct mlx5e_dcbx *dcbx = &priv->dcbx;
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if (mode & DCB_CAP_DCBX_LLD_MANAGED)
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return 1;
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if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
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if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
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return 0;
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/* set dcbx to fw controlled */
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if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
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dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
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dcbx->cap &= ~DCB_CAP_DCBX_HOST;
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return 0;
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}
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return 1;
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}
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if (!(mode & DCB_CAP_DCBX_HOST))
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return 1;
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if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
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return 1;
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dcbx->cap = mode;
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return 0;
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}
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static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
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struct ieee_maxrate *maxrate)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
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u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
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int err;
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int i;
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err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
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if (err)
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return err;
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memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
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for (i = 0; i <= mlx5_max_tc(mdev); i++) {
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switch (max_bw_unit[i]) {
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case MLX5_100_MBPS_UNIT:
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maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
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break;
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case MLX5_GBPS_UNIT:
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maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
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break;
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case MLX5_BW_NO_LIMIT:
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break;
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default:
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WARN(true, "non-supported BW unit");
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break;
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}
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}
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return 0;
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}
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static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
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struct ieee_maxrate *maxrate)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5_core_dev *mdev = priv->mdev;
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u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
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u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
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__u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
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int i;
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memset(max_bw_value, 0, sizeof(max_bw_value));
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memset(max_bw_unit, 0, sizeof(max_bw_unit));
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for (i = 0; i <= mlx5_max_tc(mdev); i++) {
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if (!maxrate->tc_maxrate[i]) {
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max_bw_unit[i] = MLX5_BW_NO_LIMIT;
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continue;
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}
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if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
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max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
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MLX5E_100MB);
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max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
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max_bw_unit[i] = MLX5_100_MBPS_UNIT;
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} else {
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max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
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MLX5E_1GB);
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max_bw_unit[i] = MLX5_GBPS_UNIT;
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}
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}
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return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
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}
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static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
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{
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struct mlx5e_priv *priv = netdev_priv(netdev);
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struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
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struct mlx5_core_dev *mdev = priv->mdev;
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struct ieee_ets ets;
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struct ieee_pfc pfc;
|
|
int err = -EOPNOTSUPP;
|
|
int i;
|
|
|
|
if (!MLX5_CAP_GEN(mdev, ets))
|
|
goto out;
|
|
|
|
memset(&ets, 0, sizeof(ets));
|
|
memset(&pfc, 0, sizeof(pfc));
|
|
|
|
ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
|
|
for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
|
|
ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
|
|
ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
|
|
ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
|
|
ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
|
|
}
|
|
|
|
err = mlx5e_dbcnl_validate_ets(netdev, &ets);
|
|
if (err) {
|
|
netdev_err(netdev,
|
|
"%s, Failed to validate ETS: %d\n", __func__, err);
|
|
goto out;
|
|
}
|
|
|
|
err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
|
|
if (err) {
|
|
netdev_err(netdev,
|
|
"%s, Failed to set ETS: %d\n", __func__, err);
|
|
goto out;
|
|
}
|
|
|
|
/* Set PFC */
|
|
pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
|
|
if (!cee_cfg->pfc_enable)
|
|
pfc.pfc_en = 0;
|
|
else
|
|
for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
|
|
pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
|
|
|
|
err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
|
|
if (err) {
|
|
netdev_err(netdev,
|
|
"%s, Failed to set PFC: %d\n", __func__, err);
|
|
goto out;
|
|
}
|
|
out:
|
|
return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
|
|
}
|
|
|
|
static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
|
|
{
|
|
return MLX5E_CEE_STATE_UP;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
|
|
u8 *perm_addr)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
|
|
if (!perm_addr)
|
|
return;
|
|
|
|
memset(perm_addr, 0xff, MAX_ADDR_LEN);
|
|
|
|
mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
|
|
}
|
|
|
|
static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
|
|
int priority, u8 prio_type,
|
|
u8 pgid, u8 bw_pct, u8 up_map)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
|
|
|
|
if (priority >= CEE_DCBX_MAX_PRIO) {
|
|
netdev_err(netdev,
|
|
"%s, priority is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (pgid >= CEE_DCBX_MAX_PGS) {
|
|
netdev_err(netdev,
|
|
"%s, priority group is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
cee_cfg->prio_to_pg_map[priority] = pgid;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
|
|
int pgid, u8 bw_pct)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
|
|
|
|
if (pgid >= CEE_DCBX_MAX_PGS) {
|
|
netdev_err(netdev,
|
|
"%s, priority group is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
cee_cfg->pg_bw_pct[pgid] = bw_pct;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
|
|
int priority, u8 *prio_type,
|
|
u8 *pgid, u8 *bw_pct, u8 *up_map)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5_core_dev *mdev = priv->mdev;
|
|
|
|
if (!MLX5_CAP_GEN(priv->mdev, ets)) {
|
|
netdev_err(netdev, "%s, ets is not supported\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (priority >= CEE_DCBX_MAX_PRIO) {
|
|
netdev_err(netdev,
|
|
"%s, priority is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
*prio_type = 0;
|
|
*bw_pct = 0;
|
|
*up_map = 0;
|
|
|
|
if (mlx5_query_port_prio_tc(mdev, priority, pgid))
|
|
*pgid = 0;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
|
|
int pgid, u8 *bw_pct)
|
|
{
|
|
struct ieee_ets ets;
|
|
|
|
if (pgid >= CEE_DCBX_MAX_PGS) {
|
|
netdev_err(netdev,
|
|
"%s, priority group is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
mlx5e_dcbnl_ieee_getets(netdev, &ets);
|
|
*bw_pct = ets.tc_tx_bw[pgid];
|
|
}
|
|
|
|
static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
|
|
int priority, u8 setting)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
|
|
|
|
if (priority >= CEE_DCBX_MAX_PRIO) {
|
|
netdev_err(netdev,
|
|
"%s, priority is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (setting > 1)
|
|
return;
|
|
|
|
cee_cfg->pfc_setting[priority] = setting;
|
|
}
|
|
|
|
static int
|
|
mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
|
|
int priority, u8 *setting)
|
|
{
|
|
struct ieee_pfc pfc;
|
|
int err;
|
|
|
|
err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
|
|
|
|
if (err)
|
|
*setting = 0;
|
|
else
|
|
*setting = (pfc.pfc_en >> priority) & 0x01;
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
|
|
int priority, u8 *setting)
|
|
{
|
|
if (priority >= CEE_DCBX_MAX_PRIO) {
|
|
netdev_err(netdev,
|
|
"%s, priority is out of range\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (!setting)
|
|
return;
|
|
|
|
mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
|
|
}
|
|
|
|
static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
|
|
int capid, u8 *cap)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5_core_dev *mdev = priv->mdev;
|
|
u8 rval = 0;
|
|
|
|
switch (capid) {
|
|
case DCB_CAP_ATTR_PG:
|
|
*cap = true;
|
|
break;
|
|
case DCB_CAP_ATTR_PFC:
|
|
*cap = true;
|
|
break;
|
|
case DCB_CAP_ATTR_UP2TC:
|
|
*cap = false;
|
|
break;
|
|
case DCB_CAP_ATTR_PG_TCS:
|
|
*cap = 1 << mlx5_max_tc(mdev);
|
|
break;
|
|
case DCB_CAP_ATTR_PFC_TCS:
|
|
*cap = 1 << mlx5_max_tc(mdev);
|
|
break;
|
|
case DCB_CAP_ATTR_GSP:
|
|
*cap = false;
|
|
break;
|
|
case DCB_CAP_ATTR_BCN:
|
|
*cap = false;
|
|
break;
|
|
case DCB_CAP_ATTR_DCBX:
|
|
*cap = priv->dcbx.cap |
|
|
DCB_CAP_DCBX_VER_CEE |
|
|
DCB_CAP_DCBX_VER_IEEE;
|
|
break;
|
|
default:
|
|
*cap = 0;
|
|
rval = 1;
|
|
break;
|
|
}
|
|
|
|
return rval;
|
|
}
|
|
|
|
static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
|
|
int tcs_id, u8 *num)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5_core_dev *mdev = priv->mdev;
|
|
|
|
switch (tcs_id) {
|
|
case DCB_NUMTCS_ATTR_PG:
|
|
case DCB_NUMTCS_ATTR_PFC:
|
|
*num = mlx5_max_tc(mdev) + 1;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
|
|
{
|
|
struct ieee_pfc pfc;
|
|
|
|
if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
|
|
return MLX5E_CEE_STATE_DOWN;
|
|
|
|
return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
|
|
}
|
|
|
|
static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
|
|
{
|
|
struct mlx5e_priv *priv = netdev_priv(netdev);
|
|
struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
|
|
|
|
if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
|
|
return;
|
|
|
|
cee_cfg->pfc_enable = state;
|
|
}
|
|
|
|
const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
|
|
.ieee_getets = mlx5e_dcbnl_ieee_getets,
|
|
.ieee_setets = mlx5e_dcbnl_ieee_setets,
|
|
.ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
|
|
.ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
|
|
.ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
|
|
.ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
|
|
.getdcbx = mlx5e_dcbnl_getdcbx,
|
|
.setdcbx = mlx5e_dcbnl_setdcbx,
|
|
|
|
/* CEE interfaces */
|
|
.setall = mlx5e_dcbnl_setall,
|
|
.getstate = mlx5e_dcbnl_getstate,
|
|
.getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
|
|
|
|
.setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
|
|
.setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
|
|
.getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
|
|
.getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
|
|
|
|
.setpfccfg = mlx5e_dcbnl_setpfccfg,
|
|
.getpfccfg = mlx5e_dcbnl_getpfccfg,
|
|
.getcap = mlx5e_dcbnl_getcap,
|
|
.getnumtcs = mlx5e_dcbnl_getnumtcs,
|
|
.getpfcstate = mlx5e_dcbnl_getpfcstate,
|
|
.setpfcstate = mlx5e_dcbnl_setpfcstate,
|
|
};
|
|
|
|
static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
|
|
enum mlx5_dcbx_oper_mode *mode)
|
|
{
|
|
u32 out[MLX5_ST_SZ_DW(dcbx_param)];
|
|
|
|
*mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
|
|
|
|
if (!mlx5_query_port_dcbx_param(priv->mdev, out))
|
|
*mode = MLX5_GET(dcbx_param, out, version_oper);
|
|
|
|
/* From driver's point of view, we only care if the mode
|
|
* is host (HOST) or non-host (AUTO)
|
|
*/
|
|
if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
|
|
*mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
|
|
}
|
|
|
|
static void mlx5e_ets_init(struct mlx5e_priv *priv)
|
|
{
|
|
int i;
|
|
struct ieee_ets ets;
|
|
|
|
if (!MLX5_CAP_GEN(priv->mdev, ets))
|
|
return;
|
|
|
|
memset(&ets, 0, sizeof(ets));
|
|
ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
|
|
for (i = 0; i < ets.ets_cap; i++) {
|
|
ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
|
|
ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
|
|
ets.prio_tc[i] = i;
|
|
}
|
|
|
|
/* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
|
|
ets.prio_tc[0] = 1;
|
|
ets.prio_tc[1] = 0;
|
|
|
|
mlx5e_dcbnl_ieee_setets_core(priv, &ets);
|
|
}
|
|
|
|
void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
|
|
{
|
|
struct mlx5e_dcbx *dcbx = &priv->dcbx;
|
|
|
|
if (!MLX5_CAP_GEN(priv->mdev, qos))
|
|
return;
|
|
|
|
if (MLX5_CAP_GEN(priv->mdev, dcbx))
|
|
mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
|
|
|
|
priv->dcbx.cap = DCB_CAP_DCBX_VER_CEE |
|
|
DCB_CAP_DCBX_VER_IEEE;
|
|
if (priv->dcbx.mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
|
|
priv->dcbx.cap |= DCB_CAP_DCBX_HOST;
|
|
|
|
mlx5e_ets_init(priv);
|
|
}
|