5983faf942
* 'tty-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (65 commits) tty: serial: imx: move del_timer_sync() to avoid potential deadlock imx: add polled io uart methods imx: Add save/restore functions for UART control regs serial/imx: let probing fail for the dt case without a valid alias serial/imx: propagate error from of_alias_get_id instead of using -ENODEV tty: serial: imx: Allow UART to be a source for wakeup serial: driver for m32 arch should not have DEC alpha errata serial/documentation: fix documented name of DCD cpp symbol atmel_serial: fix spinlock lockup in RS485 code tty: Fix memory leak in virtual console when enable unicode translation serial: use DIV_ROUND_CLOSEST instead of open coding it serial: add support for 400 and 800 v3 series Titan cards serial: bfin-uart: Remove ASYNC_CTS_FLOW flag for hardware automatic CTS. serial: bfin-uart: Enable hardware automatic CTS only when CTS pin is available. serial: make FSL errata depend on 8250_CONSOLE, not just 8250 serial: add irq handler for Freescale 16550 errata. serial: manually inline serial8250_handle_port serial: make 8250 timeout use the specified IRQ handler serial: export the key functions for an 8250 IRQ handler serial: clean up parameter passing for 8250 Rx IRQ handling ...
82 lines
2 KiB
C
82 lines
2 KiB
C
/*
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* mrst.h: Intel Moorestown platform specific setup code
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*
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* (C) Copyright 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _ASM_X86_MRST_H
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#define _ASM_X86_MRST_H
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#include <linux/sfi.h>
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extern int pci_mrst_init(void);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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extern int sfi_mrtc_num;
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extern struct sfi_rtc_table_entry sfi_mrtc_array[];
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum mrst_cpu_type {
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MRST_CPU_CHIP_LINCROFT = 1,
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MRST_CPU_CHIP_PENWELL,
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};
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extern enum mrst_cpu_type __mrst_cpu_chip;
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#ifdef CONFIG_X86_INTEL_MID
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static inline enum mrst_cpu_type mrst_identify_cpu(void)
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{
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return __mrst_cpu_chip;
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}
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#else /* !CONFIG_X86_INTEL_MID */
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#define mrst_identify_cpu() (0)
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#endif /* !CONFIG_X86_INTEL_MID */
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enum mrst_timer_options {
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MRST_TIMER_DEFAULT,
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MRST_TIMER_APBT_ONLY,
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MRST_TIMER_LAPIC_APBT,
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};
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extern enum mrst_timer_options mrst_timer_options;
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/*
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* Penwell uses spread spectrum clock, so the freq number is not exactly
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* the same as reported by MSR based on SDM.
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*/
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#define PENWELL_FSB_FREQ_83SKU 83200
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#define PENWELL_FSB_FREQ_100SKU 99840
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern struct console early_mrst_console;
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extern void mrst_early_console_init(void);
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extern struct console early_hsu_console;
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extern void hsu_early_console_init(const char *);
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extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ (1024)
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/*#define MRST_VRTC_PGOFFSET (0xc00) */
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extern void mrst_rtc_init(void);
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#endif /* _ASM_X86_MRST_H */
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