07ed1eed52
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Fugang Duan <B38611@freescale.com>
138 lines
2.8 KiB
Plaintext
138 lines
2.8 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "VF610 Tower Board";
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compatible = "fsl,vf610-twr", "fsl,vf610";
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chosen {
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bootargs = "console=ttyLP1,115200";
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};
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memory {
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reg = <0x80000000 0x8000000>;
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};
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clocks {
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audio_ext {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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};
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enet_ext {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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};
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&dspi0 {
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bus-num = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi0>;
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status = "okay";
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sflash: at26df081a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at26df081a";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&fec0 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec0>;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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};
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&iomuxc {
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vf610-twr {
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pinctrl_dspi0: dspi0grp {
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fsl,pins = <
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VF610_PAD_PTB19__DSPI0_CS0 0x1182
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VF610_PAD_PTB20__DSPI0_SIN 0x1181
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VF610_PAD_PTB21__DSPI0_SOUT 0x1182
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VF610_PAD_PTB22__DSPI0_SCK 0x1182
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>;
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};
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pinctrl_fec0: fec0grp {
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fsl,pins = <
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VF610_PAD_PTA6__RMII_CLKIN 0x30d1
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VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
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VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
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VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
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VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
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VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
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VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
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VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
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VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
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VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
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VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
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VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
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VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
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VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
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VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
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VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
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VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
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>;
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};
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pinctrl_i2c0: i2c0grp {
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fsl,pins = <
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VF610_PAD_PTB14__I2C0_SCL 0x30d3
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VF610_PAD_PTB15__I2C0_SDA 0x30d3
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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VF610_PAD_PTB4__UART1_TX 0x21a2
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VF610_PAD_PTB5__UART1_RX 0x21a1
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>;
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};
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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