![James Hogan](/assets/img/avatar_default.png)
Scratch cop0 registers are needed by KVM to be able to save/restore all the GPRs, including k0/k1, and for storing the VCPU pointer. However no registers are universally suitable for these purposes, so the decision should be made at runtime. Until now, we've used DDATA_LO to store the VCPU pointer, and ErrorEPC as a temporary. It could be argued that this is abuse of those registers, and DDATA_LO is known not to be usable on certain implementations (Cavium Octeon). If KScratch registers are present, use them instead. We save & restore the temporary register in addition to the VCPU pointer register when using a KScratch register for it, as it may be used for normal host TLB handling too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim KrÄmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
681 lines
18 KiB
C
681 lines
18 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Generation of main entry point for the guest, exception handling.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*
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* Copyright (C) 2016 Imagination Technologies Ltd.
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*/
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#include <linux/kvm_host.h>
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#include <asm/msa.h>
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#include <asm/setup.h>
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#include <asm/uasm.h>
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/* Register names */
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#define ZERO 0
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#define AT 1
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#define V0 2
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#define V1 3
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#define A0 4
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#define A1 5
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
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#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
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#define T0 12
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#define T1 13
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#define T2 14
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#define T3 15
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#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
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#define S0 16
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#define S1 17
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#define T9 25
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#define K0 26
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#define K1 27
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#define GP 28
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#define SP 29
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#define RA 31
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/* Some CP0 registers */
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#define C0_HWRENA 7, 0
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#define C0_BADVADDR 8, 0
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#define C0_ENTRYHI 10, 0
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#define C0_STATUS 12, 0
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#define C0_CAUSE 13, 0
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#define C0_EPC 14, 0
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#define C0_EBASE 15, 1
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#define C0_CONFIG5 16, 5
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#define C0_DDATA_LO 28, 3
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#define C0_ERROREPC 30, 0
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#define CALLFRAME_SIZ 32
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static unsigned int scratch_vcpu[2] = { C0_DDATA_LO };
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static unsigned int scratch_tmp[2] = { C0_ERROREPC };
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enum label_id {
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label_fpu_1 = 1,
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label_msa_1,
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label_return_to_host,
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label_kernel_asid,
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};
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UASM_L_LA(_fpu_1)
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UASM_L_LA(_msa_1)
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UASM_L_LA(_return_to_host)
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UASM_L_LA(_kernel_asid)
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static void *kvm_mips_build_enter_guest(void *addr);
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static void *kvm_mips_build_ret_from_exit(void *addr);
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static void *kvm_mips_build_ret_to_guest(void *addr);
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static void *kvm_mips_build_ret_to_host(void *addr);
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/**
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* kvm_mips_entry_setup() - Perform global setup for entry code.
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*
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* Perform global setup for entry code, such as choosing a scratch register.
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*
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* Returns: 0 on success.
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* -errno on failure.
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*/
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int kvm_mips_entry_setup(void)
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{
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/*
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* We prefer to use KScratchN registers if they are available over the
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* defaults above, which may not work on all cores.
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*/
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unsigned int kscratch_mask = cpu_data[0].kscratch_mask & 0xfc;
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/* Pick a scratch register for storing VCPU */
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if (kscratch_mask) {
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scratch_vcpu[0] = 31;
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scratch_vcpu[1] = ffs(kscratch_mask) - 1;
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kscratch_mask &= ~BIT(scratch_vcpu[1]);
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}
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/* Pick a scratch register to use as a temp for saving state */
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if (kscratch_mask) {
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scratch_tmp[0] = 31;
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scratch_tmp[1] = ffs(kscratch_mask) - 1;
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kscratch_mask &= ~BIT(scratch_tmp[1]);
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}
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return 0;
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}
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static void kvm_mips_build_save_scratch(u32 **p, unsigned int tmp,
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unsigned int frame)
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{
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/* Save the VCPU scratch register value in cp0_epc of the stack frame */
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uasm_i_mfc0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
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UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
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/* Save the temp scratch register value in cp0_cause of stack frame */
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if (scratch_tmp[0] == 31) {
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uasm_i_mfc0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
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UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
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}
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}
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static void kvm_mips_build_restore_scratch(u32 **p, unsigned int tmp,
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unsigned int frame)
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{
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/*
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* Restore host scratch register values saved by
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* kvm_mips_build_save_scratch().
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*/
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UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame);
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uasm_i_mtc0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]);
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if (scratch_tmp[0] == 31) {
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UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame);
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uasm_i_mtc0(p, tmp, scratch_tmp[0], scratch_tmp[1]);
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}
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}
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/**
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* kvm_mips_build_vcpu_run() - Assemble function to start running a guest VCPU.
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* @addr: Address to start writing code.
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*
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* Assemble the start of the vcpu_run function to run a guest VCPU. The function
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* conforms to the following prototype:
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*
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* int vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
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*
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* The exit from the guest and return to the caller is handled by the code
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* generated by kvm_mips_build_ret_to_host().
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*
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* Returns: Next address after end of written function.
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*/
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void *kvm_mips_build_vcpu_run(void *addr)
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{
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u32 *p = addr;
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unsigned int i;
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/*
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* A0: run
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* A1: vcpu
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*/
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/* k0/k1 not being used in host kernel context */
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uasm_i_addiu(&p, K1, SP, -(int)sizeof(struct pt_regs));
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for (i = 16; i < 32; ++i) {
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if (i == 24)
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i = 28;
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UASM_i_SW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
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}
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/* Save hi/lo */
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uasm_i_mflo(&p, V0);
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UASM_i_SW(&p, V0, offsetof(struct pt_regs, lo), K1);
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uasm_i_mfhi(&p, V1);
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UASM_i_SW(&p, V1, offsetof(struct pt_regs, hi), K1);
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/* Save host status */
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uasm_i_mfc0(&p, V0, C0_STATUS);
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UASM_i_SW(&p, V0, offsetof(struct pt_regs, cp0_status), K1);
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/* Save scratch registers, will be used to store pointer to vcpu etc */
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kvm_mips_build_save_scratch(&p, V1, K1);
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/* VCPU scratch register has pointer to vcpu */
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uasm_i_mtc0(&p, A1, scratch_vcpu[0], scratch_vcpu[1]);
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/* Offset into vcpu->arch */
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uasm_i_addiu(&p, K1, A1, offsetof(struct kvm_vcpu, arch));
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/*
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* Save the host stack to VCPU, used for exception processing
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* when we exit from the Guest
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*/
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UASM_i_SW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
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/* Save the kernel gp as well */
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UASM_i_SW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
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/*
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* Setup status register for running the guest in UM, interrupts
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* are disabled
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*/
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UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV);
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uasm_i_mtc0(&p, K0, C0_STATUS);
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uasm_i_ehb(&p);
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/* load up the new EBASE */
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UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
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uasm_i_mtc0(&p, K0, C0_EBASE);
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/*
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* Now that the new EBASE has been loaded, unset BEV, set
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* interrupt mask as it was but make sure that timer interrupts
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* are enabled
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*/
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uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE);
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uasm_i_andi(&p, V0, V0, ST0_IM);
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uasm_i_or(&p, K0, K0, V0);
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uasm_i_mtc0(&p, K0, C0_STATUS);
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uasm_i_ehb(&p);
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p = kvm_mips_build_enter_guest(p);
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return p;
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}
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/**
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* kvm_mips_build_enter_guest() - Assemble code to resume guest execution.
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* @addr: Address to start writing code.
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*
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* Assemble the code to resume guest execution. This code is common between the
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* initial entry into the guest from the host, and returning from the exit
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* handler back to the guest.
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*
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* Returns: Next address after end of written function.
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*/
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static void *kvm_mips_build_enter_guest(void *addr)
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{
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u32 *p = addr;
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unsigned int i;
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struct uasm_label labels[2];
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struct uasm_reloc relocs[2];
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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/* Set Guest EPC */
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UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1);
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uasm_i_mtc0(&p, T0, C0_EPC);
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/* Set the ASID for the Guest Kernel */
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UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1);
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UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]),
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T0);
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uasm_i_andi(&p, T0, T0, KSU_USER | ST0_ERL | ST0_EXL);
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uasm_i_xori(&p, T0, T0, KSU_USER);
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uasm_il_bnez(&p, &r, T0, label_kernel_asid);
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uasm_i_addiu(&p, T1, K1,
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offsetof(struct kvm_vcpu_arch, guest_kernel_asid));
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/* else user */
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uasm_i_addiu(&p, T1, K1,
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offsetof(struct kvm_vcpu_arch, guest_user_asid));
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uasm_l_kernel_asid(&l, p);
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/* t1: contains the base of the ASID array, need to get the cpu id */
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/* smp_processor_id */
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UASM_i_LW(&p, T2, offsetof(struct thread_info, cpu), GP);
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/* x4 */
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uasm_i_sll(&p, T2, T2, 2);
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UASM_i_ADDU(&p, T3, T1, T2);
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UASM_i_LW(&p, K0, 0, T3);
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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/* x sizeof(struct cpuinfo_mips)/4 */
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uasm_i_addiu(&p, T3, ZERO, sizeof(struct cpuinfo_mips)/4);
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uasm_i_mul(&p, T2, T2, T3);
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UASM_i_LA_mostly(&p, AT, (long)&cpu_data[0].asid_mask);
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UASM_i_ADDU(&p, AT, AT, T2);
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UASM_i_LW(&p, T2, uasm_rel_lo((long)&cpu_data[0].asid_mask), AT);
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uasm_i_and(&p, K0, K0, T2);
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#else
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uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID);
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#endif
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uasm_i_mtc0(&p, K0, C0_ENTRYHI);
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uasm_i_ehb(&p);
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/* Disable RDHWR access */
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uasm_i_mtc0(&p, ZERO, C0_HWRENA);
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/* load the guest context from VCPU and return */
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for (i = 1; i < 32; ++i) {
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/* Guest k0/k1 loaded later */
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if (i == K0 || i == K1)
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continue;
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UASM_i_LW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
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}
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/* Restore hi/lo */
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UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1);
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uasm_i_mthi(&p, K0);
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UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1);
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uasm_i_mtlo(&p, K0);
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/* Restore the guest's k0/k1 registers */
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UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
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UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
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/* Jump to guest */
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uasm_i_eret(&p);
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uasm_resolve_relocs(relocs, labels);
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return p;
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}
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/**
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* kvm_mips_build_exception() - Assemble first level guest exception handler.
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* @addr: Address to start writing code.
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*
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* Assemble exception vector code for guest execution. The generated vector will
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* jump to the common exception handler generated by kvm_mips_build_exit().
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*
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* Returns: Next address after end of written function.
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*/
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void *kvm_mips_build_exception(void *addr)
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{
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u32 *p = addr;
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/* Save guest k0 */
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uasm_i_mtc0(&p, K0, scratch_tmp[0], scratch_tmp[1]);
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uasm_i_ehb(&p);
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/* Get EBASE */
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uasm_i_mfc0(&p, K0, C0_EBASE);
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/* Get rid of CPUNum */
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uasm_i_srl(&p, K0, K0, 10);
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uasm_i_sll(&p, K0, K0, 10);
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/* Save k1 @ offset 0x3000 */
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UASM_i_SW(&p, K1, 0x3000, K0);
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/* Exception handler is installed @ offset 0x2000 */
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uasm_i_addiu(&p, K0, K0, 0x2000);
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/* Jump to the function */
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uasm_i_jr(&p, K0);
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uasm_i_nop(&p);
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return p;
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}
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/**
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* kvm_mips_build_exit() - Assemble common guest exit handler.
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* @addr: Address to start writing code.
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*
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* Assemble the generic guest exit handling code. This is called by the
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* exception vectors (generated by kvm_mips_build_exception()), and calls
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* kvm_mips_handle_exit(), then either resumes the guest or returns to the host
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* depending on the return value.
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*
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* Returns: Next address after end of written function.
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*/
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void *kvm_mips_build_exit(void *addr)
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{
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u32 *p = addr;
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unsigned int i;
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struct uasm_label labels[3];
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struct uasm_reloc relocs[3];
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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/*
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* Generic Guest exception handler. We end up here when the guest
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* does something that causes a trap to kernel mode.
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*/
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/* Get the VCPU pointer from the scratch register */
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uasm_i_mfc0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]);
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uasm_i_addiu(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
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/* Start saving Guest context to VCPU */
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for (i = 0; i < 32; ++i) {
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/* Guest k0/k1 saved later */
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if (i == K0 || i == K1)
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continue;
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UASM_i_SW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1);
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}
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/* We need to save hi/lo and restore them on the way out */
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uasm_i_mfhi(&p, T0);
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UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1);
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uasm_i_mflo(&p, T0);
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UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1);
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/* Finally save guest k0/k1 to VCPU */
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uasm_i_mfc0(&p, T0, scratch_tmp[0], scratch_tmp[1]);
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UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1);
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/* Get GUEST k1 and save it in VCPU */
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uasm_i_addiu(&p, T1, ZERO, ~0x2ff);
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uasm_i_mfc0(&p, T0, C0_EBASE);
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uasm_i_and(&p, T0, T0, T1);
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UASM_i_LW(&p, T0, 0x3000, T0);
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UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1);
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/* Now that context has been saved, we can use other registers */
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/* Restore vcpu */
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uasm_i_mfc0(&p, A1, scratch_vcpu[0], scratch_vcpu[1]);
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uasm_i_move(&p, S1, A1);
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/* Restore run (vcpu->run) */
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UASM_i_LW(&p, A0, offsetof(struct kvm_vcpu, run), A1);
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/* Save pointer to run in s0, will be saved by the compiler */
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uasm_i_move(&p, S0, A0);
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/*
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* Save Host level EPC, BadVaddr and Cause to VCPU, useful to process
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* the exception
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*/
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uasm_i_mfc0(&p, K0, C0_EPC);
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UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1);
|
|
|
|
uasm_i_mfc0(&p, K0, C0_BADVADDR);
|
|
UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr),
|
|
K1);
|
|
|
|
uasm_i_mfc0(&p, K0, C0_CAUSE);
|
|
uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1);
|
|
|
|
/* Now restore the host state just enough to run the handlers */
|
|
|
|
/* Switch EBASE to the one used by Linux */
|
|
/* load up the host EBASE */
|
|
uasm_i_mfc0(&p, V0, C0_STATUS);
|
|
|
|
uasm_i_lui(&p, AT, ST0_BEV >> 16);
|
|
uasm_i_or(&p, K0, V0, AT);
|
|
|
|
uasm_i_mtc0(&p, K0, C0_STATUS);
|
|
uasm_i_ehb(&p);
|
|
|
|
UASM_i_LA_mostly(&p, K0, (long)&ebase);
|
|
UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0);
|
|
uasm_i_mtc0(&p, K0, C0_EBASE);
|
|
|
|
if (raw_cpu_has_fpu) {
|
|
/*
|
|
* If FPU is enabled, save FCR31 and clear it so that later
|
|
* ctc1's don't trigger FPE for pending exceptions.
|
|
*/
|
|
uasm_i_lui(&p, AT, ST0_CU1 >> 16);
|
|
uasm_i_and(&p, V1, V0, AT);
|
|
uasm_il_beqz(&p, &r, V1, label_fpu_1);
|
|
uasm_i_nop(&p);
|
|
uasm_i_cfc1(&p, T0, 31);
|
|
uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31),
|
|
K1);
|
|
uasm_i_ctc1(&p, ZERO, 31);
|
|
uasm_l_fpu_1(&l, p);
|
|
}
|
|
|
|
if (cpu_has_msa) {
|
|
/*
|
|
* If MSA is enabled, save MSACSR and clear it so that later
|
|
* instructions don't trigger MSAFPE for pending exceptions.
|
|
*/
|
|
uasm_i_mfc0(&p, T0, C0_CONFIG5);
|
|
uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */
|
|
uasm_il_beqz(&p, &r, T0, label_msa_1);
|
|
uasm_i_nop(&p);
|
|
uasm_i_cfcmsa(&p, T0, MSA_CSR);
|
|
uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr),
|
|
K1);
|
|
uasm_i_ctcmsa(&p, MSA_CSR, ZERO);
|
|
uasm_l_msa_1(&l, p);
|
|
}
|
|
|
|
/* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
|
|
uasm_i_addiu(&p, AT, ZERO, ~(ST0_EXL | KSU_USER | ST0_IE));
|
|
uasm_i_and(&p, V0, V0, AT);
|
|
uasm_i_lui(&p, AT, ST0_CU0 >> 16);
|
|
uasm_i_or(&p, V0, V0, AT);
|
|
uasm_i_mtc0(&p, V0, C0_STATUS);
|
|
uasm_i_ehb(&p);
|
|
|
|
/* Load up host GP */
|
|
UASM_i_LW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1);
|
|
|
|
/* Need a stack before we can jump to "C" */
|
|
UASM_i_LW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1);
|
|
|
|
/* Saved host state */
|
|
uasm_i_addiu(&p, SP, SP, -(int)sizeof(struct pt_regs));
|
|
|
|
/*
|
|
* XXXKYMA do we need to load the host ASID, maybe not because the
|
|
* kernel entries are marked GLOBAL, need to verify
|
|
*/
|
|
|
|
/* Restore host scratch registers, as we'll have clobbered them */
|
|
kvm_mips_build_restore_scratch(&p, K0, SP);
|
|
|
|
/* Restore RDHWR access */
|
|
UASM_i_LA_mostly(&p, K0, (long)&hwrena);
|
|
uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
|
|
uasm_i_mtc0(&p, K0, C0_HWRENA);
|
|
|
|
/* Jump to handler */
|
|
/*
|
|
* XXXKYMA: not sure if this is safe, how large is the stack??
|
|
* Now jump to the kvm_mips_handle_exit() to see if we can deal
|
|
* with this in the kernel
|
|
*/
|
|
UASM_i_LA(&p, T9, (unsigned long)kvm_mips_handle_exit);
|
|
uasm_i_jalr(&p, RA, T9);
|
|
uasm_i_addiu(&p, SP, SP, -CALLFRAME_SIZ);
|
|
|
|
uasm_resolve_relocs(relocs, labels);
|
|
|
|
p = kvm_mips_build_ret_from_exit(p);
|
|
|
|
return p;
|
|
}
|
|
|
|
/**
|
|
* kvm_mips_build_ret_from_exit() - Assemble guest exit return handler.
|
|
* @addr: Address to start writing code.
|
|
*
|
|
* Assemble the code to handle the return from kvm_mips_handle_exit(), either
|
|
* resuming the guest or returning to the host depending on the return value.
|
|
*
|
|
* Returns: Next address after end of written function.
|
|
*/
|
|
static void *kvm_mips_build_ret_from_exit(void *addr)
|
|
{
|
|
u32 *p = addr;
|
|
struct uasm_label labels[2];
|
|
struct uasm_reloc relocs[2];
|
|
struct uasm_label *l = labels;
|
|
struct uasm_reloc *r = relocs;
|
|
|
|
memset(labels, 0, sizeof(labels));
|
|
memset(relocs, 0, sizeof(relocs));
|
|
|
|
/* Return from handler Make sure interrupts are disabled */
|
|
uasm_i_di(&p, ZERO);
|
|
uasm_i_ehb(&p);
|
|
|
|
/*
|
|
* XXXKYMA: k0/k1 could have been blown away if we processed
|
|
* an exception while we were handling the exception from the
|
|
* guest, reload k1
|
|
*/
|
|
|
|
uasm_i_move(&p, K1, S1);
|
|
uasm_i_addiu(&p, K1, K1, offsetof(struct kvm_vcpu, arch));
|
|
|
|
/*
|
|
* Check return value, should tell us if we are returning to the
|
|
* host (handle I/O etc)or resuming the guest
|
|
*/
|
|
uasm_i_andi(&p, T0, V0, RESUME_HOST);
|
|
uasm_il_bnez(&p, &r, T0, label_return_to_host);
|
|
uasm_i_nop(&p);
|
|
|
|
p = kvm_mips_build_ret_to_guest(p);
|
|
|
|
uasm_l_return_to_host(&l, p);
|
|
p = kvm_mips_build_ret_to_host(p);
|
|
|
|
uasm_resolve_relocs(relocs, labels);
|
|
|
|
return p;
|
|
}
|
|
|
|
/**
|
|
* kvm_mips_build_ret_to_guest() - Assemble code to return to the guest.
|
|
* @addr: Address to start writing code.
|
|
*
|
|
* Assemble the code to handle return from the guest exit handler
|
|
* (kvm_mips_handle_exit()) back to the guest.
|
|
*
|
|
* Returns: Next address after end of written function.
|
|
*/
|
|
static void *kvm_mips_build_ret_to_guest(void *addr)
|
|
{
|
|
u32 *p = addr;
|
|
|
|
/* Put the saved pointer to vcpu (s1) back into the scratch register */
|
|
uasm_i_mtc0(&p, S1, scratch_vcpu[0], scratch_vcpu[1]);
|
|
|
|
/* Load up the Guest EBASE to minimize the window where BEV is set */
|
|
UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1);
|
|
|
|
/* Switch EBASE back to the one used by KVM */
|
|
uasm_i_mfc0(&p, V1, C0_STATUS);
|
|
uasm_i_lui(&p, AT, ST0_BEV >> 16);
|
|
uasm_i_or(&p, K0, V1, AT);
|
|
uasm_i_mtc0(&p, K0, C0_STATUS);
|
|
uasm_i_ehb(&p);
|
|
uasm_i_mtc0(&p, T0, C0_EBASE);
|
|
|
|
/* Setup status register for running guest in UM */
|
|
uasm_i_ori(&p, V1, V1, ST0_EXL | KSU_USER | ST0_IE);
|
|
UASM_i_LA(&p, AT, ~(ST0_CU0 | ST0_MX));
|
|
uasm_i_and(&p, V1, V1, AT);
|
|
uasm_i_mtc0(&p, V1, C0_STATUS);
|
|
uasm_i_ehb(&p);
|
|
|
|
p = kvm_mips_build_enter_guest(p);
|
|
|
|
return p;
|
|
}
|
|
|
|
/**
|
|
* kvm_mips_build_ret_to_host() - Assemble code to return to the host.
|
|
* @addr: Address to start writing code.
|
|
*
|
|
* Assemble the code to handle return from the guest exit handler
|
|
* (kvm_mips_handle_exit()) back to the host, i.e. to the caller of the vcpu_run
|
|
* function generated by kvm_mips_build_vcpu_run().
|
|
*
|
|
* Returns: Next address after end of written function.
|
|
*/
|
|
static void *kvm_mips_build_ret_to_host(void *addr)
|
|
{
|
|
u32 *p = addr;
|
|
unsigned int i;
|
|
|
|
/* EBASE is already pointing to Linux */
|
|
UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, host_stack), K1);
|
|
uasm_i_addiu(&p, K1, K1, -(int)sizeof(struct pt_regs));
|
|
|
|
/*
|
|
* r2/v0 is the return code, shift it down by 2 (arithmetic)
|
|
* to recover the err code
|
|
*/
|
|
uasm_i_sra(&p, K0, V0, 2);
|
|
uasm_i_move(&p, V0, K0);
|
|
|
|
/* Load context saved on the host stack */
|
|
for (i = 16; i < 31; ++i) {
|
|
if (i == 24)
|
|
i = 28;
|
|
UASM_i_LW(&p, i, offsetof(struct pt_regs, regs[i]), K1);
|
|
}
|
|
|
|
UASM_i_LW(&p, K0, offsetof(struct pt_regs, hi), K1);
|
|
uasm_i_mthi(&p, K0);
|
|
|
|
UASM_i_LW(&p, K0, offsetof(struct pt_regs, lo), K1);
|
|
uasm_i_mtlo(&p, K0);
|
|
|
|
/* Restore RDHWR access */
|
|
UASM_i_LA_mostly(&p, K0, (long)&hwrena);
|
|
uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0);
|
|
uasm_i_mtc0(&p, K0, C0_HWRENA);
|
|
|
|
/* Restore RA, which is the address we will return to */
|
|
UASM_i_LW(&p, RA, offsetof(struct pt_regs, regs[RA]), K1);
|
|
uasm_i_jr(&p, RA);
|
|
uasm_i_nop(&p);
|
|
|
|
return p;
|
|
}
|
|
|