f7b8156d15
The DFSR and IFSR register format is different when LPAE is enabled. In addition, DFSR and IFSR have similar definitions for the fault type. This modifies the fault code to correctly handle the new format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
29 lines
650 B
C
29 lines
650 B
C
#ifndef __ARCH_ARM_FAULT_H
|
|
#define __ARCH_ARM_FAULT_H
|
|
|
|
/*
|
|
* Fault status register encodings. We steal bit 31 for our own purposes.
|
|
*/
|
|
#define FSR_LNX_PF (1 << 31)
|
|
#define FSR_WRITE (1 << 11)
|
|
#define FSR_FS4 (1 << 10)
|
|
#define FSR_FS3_0 (15)
|
|
#define FSR_FS5_0 (0x3f)
|
|
|
|
#ifdef CONFIG_ARM_LPAE
|
|
static inline int fsr_fs(unsigned int fsr)
|
|
{
|
|
return fsr & FSR_FS5_0;
|
|
}
|
|
#else
|
|
static inline int fsr_fs(unsigned int fsr)
|
|
{
|
|
return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
|
|
}
|
|
#endif
|
|
|
|
void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
|
|
unsigned long search_exception_table(unsigned long addr);
|
|
|
|
#endif /* __ARCH_ARM_FAULT_H */
|