![Andrey Smirnov](/assets/img/avatar_default.png)
Implement .device_synchronize callback in order to be able to use dmaengine_terminate_sync() and other primitives relying on said callback. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Chris Healy <cphealy@gmail.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-imx@nxp.com Cc: dmaengine@vger.kernel.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20190731173659.14778-1-andrew.smirnov@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
498 lines
13 KiB
C
498 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* drivers/dma/fsl-edma.c
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*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* Driver for the Freescale eDMA engine with flexible channel multiplexing
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* capability for DMA request sources. The eDMA block can be found on some
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* Vybrid and Layerscape SoCs.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_dma.h>
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#include "fsl-edma-common.h"
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static void fsl_edma_synchronize(struct dma_chan *chan)
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{
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struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
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vchan_synchronize(&fsl_chan->vchan);
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}
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static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *fsl_edma = dev_id;
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unsigned int intr, ch;
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struct edma_regs *regs = &fsl_edma->regs;
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struct fsl_edma_chan *fsl_chan;
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intr = edma_readl(fsl_edma, regs->intl);
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if (!intr)
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return IRQ_NONE;
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for (ch = 0; ch < fsl_edma->n_chans; ch++) {
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if (intr & (0x1 << ch)) {
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edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
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fsl_chan = &fsl_edma->chans[ch];
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spin_lock(&fsl_chan->vchan.lock);
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if (!fsl_chan->edesc->iscyclic) {
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list_del(&fsl_chan->edesc->vdesc.node);
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vchan_cookie_complete(&fsl_chan->edesc->vdesc);
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fsl_chan->edesc = NULL;
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fsl_chan->status = DMA_COMPLETE;
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fsl_chan->idle = true;
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} else {
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vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
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}
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if (!fsl_chan->edesc)
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fsl_edma_xfer_desc(fsl_chan);
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spin_unlock(&fsl_chan->vchan.lock);
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}
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
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{
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struct fsl_edma_engine *fsl_edma = dev_id;
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unsigned int err, ch;
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struct edma_regs *regs = &fsl_edma->regs;
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err = edma_readl(fsl_edma, regs->errl);
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if (!err)
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return IRQ_NONE;
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for (ch = 0; ch < fsl_edma->n_chans; ch++) {
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if (err & (0x1 << ch)) {
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fsl_edma_disable_request(&fsl_edma->chans[ch]);
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edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
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fsl_edma->chans[ch].status = DMA_ERROR;
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fsl_edma->chans[ch].idle = true;
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}
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
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{
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if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
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return IRQ_HANDLED;
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return fsl_edma_err_handler(irq, dev_id);
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}
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static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
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struct dma_chan *chan, *_chan;
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struct fsl_edma_chan *fsl_chan;
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u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
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unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
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if (dma_spec->args_count != 2)
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return NULL;
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mutex_lock(&fsl_edma->fsl_edma_mutex);
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list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
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if (chan->client_count)
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continue;
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if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
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chan = dma_get_slave_channel(chan);
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if (chan) {
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chan->device->privatecnt++;
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fsl_chan = to_fsl_edma_chan(chan);
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fsl_chan->slave_id = dma_spec->args[1];
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fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
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true);
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mutex_unlock(&fsl_edma->fsl_edma_mutex);
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return chan;
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}
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}
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}
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mutex_unlock(&fsl_edma->fsl_edma_mutex);
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return NULL;
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}
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static int
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fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
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{
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int ret;
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fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
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if (fsl_edma->txirq < 0)
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return fsl_edma->txirq;
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fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
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if (fsl_edma->errirq < 0)
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return fsl_edma->errirq;
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if (fsl_edma->txirq == fsl_edma->errirq) {
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ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
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fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
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if (ret) {
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dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
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return ret;
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}
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} else {
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ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
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fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
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if (ret) {
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dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
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return ret;
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}
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ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
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fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
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if (ret) {
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dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
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return ret;
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}
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}
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return 0;
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}
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static int
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fsl_edma2_irq_init(struct platform_device *pdev,
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struct fsl_edma_engine *fsl_edma)
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{
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int i, ret, irq;
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int count;
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count = platform_irq_count(pdev);
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dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
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if (count <= 2) {
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dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
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return -EINVAL;
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}
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/*
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* 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
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* 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
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* For now, just simply request irq without IRQF_SHARED flag, since 16
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* channels are enough on i.mx7ulp whose M4 domain own some peripherals.
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*/
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for (i = 0; i < count; i++) {
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irq = platform_get_irq(pdev, i);
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if (irq < 0)
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return -ENXIO;
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sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
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/* The last IRQ is for eDMA err */
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if (i == count - 1)
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ret = devm_request_irq(&pdev->dev, irq,
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fsl_edma_err_handler,
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0, "eDMA2-ERR", fsl_edma);
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else
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ret = devm_request_irq(&pdev->dev, irq,
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fsl_edma_tx_handler, 0,
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fsl_edma->chans[i].chan_name,
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fsl_edma);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void fsl_edma_irq_exit(
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struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
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{
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if (fsl_edma->txirq == fsl_edma->errirq) {
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devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
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} else {
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devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
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devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
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}
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}
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static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
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{
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int i;
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for (i = 0; i < nr_clocks; i++)
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clk_disable_unprepare(fsl_edma->muxclk[i]);
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}
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static struct fsl_edma_drvdata vf610_data = {
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.version = v1,
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.dmamuxs = DMAMUX_NR,
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.setup_irq = fsl_edma_irq_init,
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};
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static struct fsl_edma_drvdata imx7ulp_data = {
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.version = v3,
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.dmamuxs = 1,
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.has_dmaclk = true,
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.setup_irq = fsl_edma2_irq_init,
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};
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static const struct of_device_id fsl_edma_dt_ids[] = {
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{ .compatible = "fsl,vf610-edma", .data = &vf610_data},
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{ .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
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static int fsl_edma_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id =
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of_match_device(fsl_edma_dt_ids, &pdev->dev);
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struct device_node *np = pdev->dev.of_node;
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struct fsl_edma_engine *fsl_edma;
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const struct fsl_edma_drvdata *drvdata = NULL;
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struct fsl_edma_chan *fsl_chan;
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struct edma_regs *regs;
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struct resource *res;
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int len, chans;
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int ret, i;
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if (of_id)
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drvdata = of_id->data;
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if (!drvdata) {
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dev_err(&pdev->dev, "unable to find driver data\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(np, "dma-channels", &chans);
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if (ret) {
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dev_err(&pdev->dev, "Can't get dma-channels.\n");
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return ret;
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}
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len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
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fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
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if (!fsl_edma)
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return -ENOMEM;
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fsl_edma->drvdata = drvdata;
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fsl_edma->n_chans = chans;
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mutex_init(&fsl_edma->fsl_edma_mutex);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(fsl_edma->membase))
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return PTR_ERR(fsl_edma->membase);
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fsl_edma_setup_regs(fsl_edma);
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regs = &fsl_edma->regs;
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if (drvdata->has_dmaclk) {
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fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
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if (IS_ERR(fsl_edma->dmaclk)) {
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dev_err(&pdev->dev, "Missing DMA block clock.\n");
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return PTR_ERR(fsl_edma->dmaclk);
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}
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ret = clk_prepare_enable(fsl_edma->dmaclk);
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if (ret) {
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dev_err(&pdev->dev, "DMA clk block failed.\n");
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return ret;
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}
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}
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for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
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char clkname[32];
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
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fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(fsl_edma->muxbase[i])) {
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/* on error: disable all previously enabled clks */
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fsl_disable_clocks(fsl_edma, i);
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return PTR_ERR(fsl_edma->muxbase[i]);
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}
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sprintf(clkname, "dmamux%d", i);
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fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
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if (IS_ERR(fsl_edma->muxclk[i])) {
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dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
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/* on error: disable all previously enabled clks */
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fsl_disable_clocks(fsl_edma, i);
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return PTR_ERR(fsl_edma->muxclk[i]);
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}
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ret = clk_prepare_enable(fsl_edma->muxclk[i]);
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if (ret)
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/* on error: disable all previously enabled clks */
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fsl_disable_clocks(fsl_edma, i);
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}
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fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
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INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
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for (i = 0; i < fsl_edma->n_chans; i++) {
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struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
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fsl_chan->edma = fsl_edma;
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fsl_chan->pm_state = RUNNING;
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fsl_chan->slave_id = 0;
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fsl_chan->idle = true;
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fsl_chan->dma_dir = DMA_NONE;
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fsl_chan->vchan.desc_free = fsl_edma_free_desc;
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vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
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edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
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fsl_edma_chan_mux(fsl_chan, 0, false);
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}
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edma_writel(fsl_edma, ~0, regs->intl);
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ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
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if (ret)
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return ret;
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dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
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dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
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fsl_edma->dma_dev.dev = &pdev->dev;
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fsl_edma->dma_dev.device_alloc_chan_resources
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= fsl_edma_alloc_chan_resources;
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fsl_edma->dma_dev.device_free_chan_resources
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= fsl_edma_free_chan_resources;
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fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
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fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
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fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
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fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
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fsl_edma->dma_dev.device_pause = fsl_edma_pause;
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fsl_edma->dma_dev.device_resume = fsl_edma_resume;
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fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
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fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
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fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
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fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
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fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
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fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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platform_set_drvdata(pdev, fsl_edma);
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ret = dma_async_device_register(&fsl_edma->dma_dev);
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if (ret) {
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dev_err(&pdev->dev,
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"Can't register Freescale eDMA engine. (%d)\n", ret);
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fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
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return ret;
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}
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ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
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if (ret) {
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dev_err(&pdev->dev,
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"Can't register Freescale eDMA of_dma. (%d)\n", ret);
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dma_async_device_unregister(&fsl_edma->dma_dev);
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fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
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return ret;
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}
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/* enable round robin arbitration */
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edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
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return 0;
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}
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static int fsl_edma_remove(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
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fsl_edma_irq_exit(pdev, fsl_edma);
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fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
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of_dma_controller_free(np);
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dma_async_device_unregister(&fsl_edma->dma_dev);
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fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
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return 0;
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}
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static int fsl_edma_suspend_late(struct device *dev)
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{
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struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
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struct fsl_edma_chan *fsl_chan;
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unsigned long flags;
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int i;
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for (i = 0; i < fsl_edma->n_chans; i++) {
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fsl_chan = &fsl_edma->chans[i];
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spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
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/* Make sure chan is idle or will force disable. */
|
|
if (unlikely(!fsl_chan->idle)) {
|
|
dev_warn(dev, "WARN: There is non-idle channel.");
|
|
fsl_edma_disable_request(fsl_chan);
|
|
fsl_edma_chan_mux(fsl_chan, 0, false);
|
|
}
|
|
|
|
fsl_chan->pm_state = SUSPENDED;
|
|
spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_edma_resume_early(struct device *dev)
|
|
{
|
|
struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
|
|
struct fsl_edma_chan *fsl_chan;
|
|
struct edma_regs *regs = &fsl_edma->regs;
|
|
int i;
|
|
|
|
for (i = 0; i < fsl_edma->n_chans; i++) {
|
|
fsl_chan = &fsl_edma->chans[i];
|
|
fsl_chan->pm_state = RUNNING;
|
|
edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
|
|
if (fsl_chan->slave_id != 0)
|
|
fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
|
|
}
|
|
|
|
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* eDMA provides the service to others, so it should be suspend late
|
|
* and resume early. When eDMA suspend, all of the clients should stop
|
|
* the DMA data transmission and let the channel idle.
|
|
*/
|
|
static const struct dev_pm_ops fsl_edma_pm_ops = {
|
|
.suspend_late = fsl_edma_suspend_late,
|
|
.resume_early = fsl_edma_resume_early,
|
|
};
|
|
|
|
static struct platform_driver fsl_edma_driver = {
|
|
.driver = {
|
|
.name = "fsl-edma",
|
|
.of_match_table = fsl_edma_dt_ids,
|
|
.pm = &fsl_edma_pm_ops,
|
|
},
|
|
.probe = fsl_edma_probe,
|
|
.remove = fsl_edma_remove,
|
|
};
|
|
|
|
static int __init fsl_edma_init(void)
|
|
{
|
|
return platform_driver_register(&fsl_edma_driver);
|
|
}
|
|
subsys_initcall(fsl_edma_init);
|
|
|
|
static void __exit fsl_edma_exit(void)
|
|
{
|
|
platform_driver_unregister(&fsl_edma_driver);
|
|
}
|
|
module_exit(fsl_edma_exit);
|
|
|
|
MODULE_ALIAS("platform:fsl-edma");
|
|
MODULE_DESCRIPTION("Freescale eDMA engine driver");
|
|
MODULE_LICENSE("GPL v2");
|