![Ulrich Hecht](/assets/img/avatar_default.png)
Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
200 lines
5 KiB
C
200 lines
5 KiB
C
/*
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* r8a7740 Core CPG Clocks
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*
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/shmobile.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/spinlock.h>
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struct r8a7740_cpg {
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struct clk_onecell_data data;
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spinlock_t lock;
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void __iomem *reg;
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};
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#define CPG_FRQCRA 0x00
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#define CPG_FRQCRB 0x04
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#define CPG_PLLC2CR 0x2c
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#define CPG_USBCKCR 0x8c
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#define CPG_FRQCRC 0xe0
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#define CLK_ENABLE_ON_INIT BIT(0)
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struct div4_clk {
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const char *name;
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unsigned int reg;
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unsigned int shift;
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int flags;
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};
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static struct div4_clk div4_clks[] = {
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{ "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
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{ "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
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{ "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
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{ "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
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{ "hp", CPG_FRQCRB, 4, 0 },
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{ "hpp", CPG_FRQCRC, 20, 0 },
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{ "usbp", CPG_FRQCRC, 16, 0 },
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{ "s", CPG_FRQCRC, 12, 0 },
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{ "zb", CPG_FRQCRC, 8, 0 },
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{ "m3", CPG_FRQCRC, 4, 0 },
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{ "cp", CPG_FRQCRC, 0, 0 },
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{ NULL, 0, 0, 0 },
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};
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static const struct clk_div_table div4_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
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{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
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{ 13, 72 }, { 14, 96 }, { 0, 0 }
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};
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static u32 cpg_mode __initdata;
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static struct clk * __init
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r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
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const char *name)
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{
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const struct clk_div_table *table = NULL;
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const char *parent_name;
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unsigned int shift, reg;
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unsigned int mult = 1;
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unsigned int div = 1;
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if (!strcmp(name, "r")) {
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switch (cpg_mode & (BIT(2) | BIT(1))) {
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case BIT(1) | BIT(2):
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/* extal1 */
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parent_name = of_clk_get_parent_name(np, 0);
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div = 2048;
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break;
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case BIT(2):
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/* extal1 */
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parent_name = of_clk_get_parent_name(np, 0);
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div = 1024;
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break;
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default:
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/* extalr */
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parent_name = of_clk_get_parent_name(np, 2);
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break;
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}
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} else if (!strcmp(name, "system")) {
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parent_name = of_clk_get_parent_name(np, 0);
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if (cpg_mode & BIT(1))
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div = 2;
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} else if (!strcmp(name, "pllc0")) {
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/* PLLC0/1 are configurable multiplier clocks. Register them as
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* fixed factor clocks for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
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parent_name = "system";
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mult = ((value >> 24) & 0x7f) + 1;
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} else if (!strcmp(name, "pllc1")) {
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u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
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parent_name = "system";
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mult = ((value >> 24) & 0x7f) + 1;
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div = 2;
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} else if (!strcmp(name, "pllc2")) {
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u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
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parent_name = "system";
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mult = ((value >> 24) & 0x3f) + 1;
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} else if (!strcmp(name, "usb24s")) {
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u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
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if (value & BIT(7))
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/* extal2 */
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parent_name = of_clk_get_parent_name(np, 1);
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else
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parent_name = "system";
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if (!(value & BIT(6)))
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div = 2;
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} else {
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struct div4_clk *c;
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for (c = div4_clks; c->name; c++) {
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if (!strcmp(name, c->name)) {
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parent_name = "pllc1";
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table = div4_div_table;
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reg = c->reg;
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shift = c->shift;
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break;
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}
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}
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if (!c->name)
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return ERR_PTR(-EINVAL);
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}
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if (!table) {
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return clk_register_fixed_factor(NULL, name, parent_name, 0,
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mult, div);
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} else {
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return clk_register_divider_table(NULL, name, parent_name, 0,
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cpg->reg + reg, shift, 4, 0,
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table, &cpg->lock);
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}
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}
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static void __init r8a7740_cpg_clocks_init(struct device_node *np)
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{
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struct r8a7740_cpg *cpg;
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struct clk **clks;
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unsigned int i;
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int num_clks;
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if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
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pr_warn("%s: missing renesas,mode property\n", __func__);
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (num_clks < 0) {
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pr_err("%s: failed to count clocks\n", __func__);
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return;
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}
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
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if (cpg == NULL || clks == NULL) {
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/* We're leaking memory on purpose, there's no point in cleaning
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* up as the system won't boot anyway.
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*/
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return;
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}
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spin_lock_init(&cpg->lock);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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if (WARN_ON(cpg->reg == NULL))
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return;
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i,
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&name);
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clk = r8a7740_cpg_register_clock(np, cpg, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clk));
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else
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cpg->data.clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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}
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CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
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r8a7740_cpg_clocks_init);
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