1a34275d34
The clocks on ti81xx are not compatible with omap3. On dm816x the clock source is a FAPLL (Flying Adder PLL), and on dm814x there seems to be an APLL (All Digital PLL). Let's fix up things for dm816x in preparation for adding the FAPLL support. As we already have a dummy ti81xx_dt_clk_init() in place, let's use that for now to avoid adding a dependency to the omap patches. Later on if somebody adds dm814x support we can split the ti81xx_dt_clk_init() clock init function as needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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static struct ti_dt_clk dm816x_clks[] = {
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DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
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DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
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DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
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DT_CLK(NULL, "mpu_ck", "mpu_ck"),
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DT_CLK(NULL, "timer1_fck", "timer1_fck"),
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DT_CLK(NULL, "timer2_fck", "timer2_fck"),
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DT_CLK(NULL, "timer3_fck", "timer3_fck"),
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DT_CLK(NULL, "timer4_fck", "timer4_fck"),
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DT_CLK(NULL, "timer5_fck", "timer5_fck"),
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DT_CLK(NULL, "timer6_fck", "timer6_fck"),
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DT_CLK(NULL, "timer7_fck", "timer7_fck"),
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DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
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DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
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DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
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DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
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DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
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DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"),
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DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
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{ .node_name = NULL },
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};
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static const char *enable_init_clks[] = {
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"ddr_pll_clk1",
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"ddr_pll_clk2",
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"ddr_pll_clk3",
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};
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int __init ti81xx_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm816x_clks);
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omap2_clk_disable_autoidle_all();
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omap2_clk_enable_init_clocks(enable_init_clks,
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ARRAY_SIZE(enable_init_clks));
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return 0;
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}
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