![Uwe Kleine-König](/assets/img/avatar_default.png)
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
310 lines
7.4 KiB
C
310 lines
7.4 KiB
C
/*
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* TI composite clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include <linux/list.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return -EINVAL;
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}
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static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return -EINVAL;
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}
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static const struct clk_ops ti_composite_divider_ops = {
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.recalc_rate = &ti_composite_recalc_rate,
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.round_rate = &ti_composite_round_rate,
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.set_rate = &ti_composite_set_rate,
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};
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static const struct clk_ops ti_composite_gate_ops = {
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.enable = &omap2_dflt_clk_enable,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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struct component_clk {
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int num_parents;
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const char **parent_names;
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struct device_node *node;
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int type;
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struct clk_hw *hw;
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struct list_head link;
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};
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static const char * const component_clk_types[] __initconst = {
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"gate", "divider", "mux"
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};
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static LIST_HEAD(component_clks);
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static struct device_node *_get_component_node(struct device_node *node, int i)
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{
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int rc;
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struct of_phandle_args clkspec;
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rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
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&clkspec);
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if (rc)
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return NULL;
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return clkspec.np;
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}
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static struct component_clk *_lookup_component(struct device_node *node)
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{
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struct component_clk *comp;
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list_for_each_entry(comp, &component_clks, link) {
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if (comp->node == node)
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return comp;
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}
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return NULL;
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}
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struct clk_hw_omap_comp {
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struct clk_hw hw;
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struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
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struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
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};
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static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
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{
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if (!clk)
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return NULL;
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if (!clk->comp_clks[idx])
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return NULL;
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return clk->comp_clks[idx]->hw;
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}
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#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
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struct clk *ti_clk_register_composite(struct ti_clk *setup)
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{
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struct ti_clk_composite *comp;
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struct clk_hw *gate;
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struct clk_hw *mux;
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struct clk_hw *div;
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int num_parents = 1;
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const char **parent_names = NULL;
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struct clk *clk;
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comp = setup->data;
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div = ti_clk_build_component_div(comp->divider);
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gate = ti_clk_build_component_gate(comp->gate);
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mux = ti_clk_build_component_mux(comp->mux);
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if (div)
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parent_names = &comp->divider->parent;
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if (gate)
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parent_names = &comp->gate->parent;
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if (mux) {
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num_parents = comp->mux->num_parents;
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parent_names = comp->mux->parents;
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}
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clk = clk_register_composite(NULL, setup->name,
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parent_names, num_parents, mux,
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&ti_clk_mux_ops, div,
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&ti_composite_divider_ops, gate,
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&ti_composite_gate_ops, 0);
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return clk;
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}
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#endif
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static void __init _register_composite(struct clk_hw *hw,
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struct device_node *node)
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{
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struct clk *clk;
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struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
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struct component_clk *comp;
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int num_parents = 0;
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const char **parent_names = NULL;
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int i;
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/* Check for presence of each component clock */
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for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
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if (!cclk->comp_nodes[i])
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continue;
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comp = _lookup_component(cclk->comp_nodes[i]);
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if (!comp) {
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pr_debug("component %s not ready for %s, retry\n",
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cclk->comp_nodes[i]->name, node->name);
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if (!ti_clk_retry_init(node, hw,
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_register_composite))
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return;
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goto cleanup;
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}
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if (cclk->comp_clks[comp->type] != NULL) {
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pr_err("duplicate component types for %s (%s)!\n",
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node->name, component_clk_types[comp->type]);
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goto cleanup;
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}
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cclk->comp_clks[comp->type] = comp;
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/* Mark this node as found */
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cclk->comp_nodes[i] = NULL;
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}
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/* All components exists, proceed with registration */
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for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
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comp = cclk->comp_clks[i];
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if (!comp)
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continue;
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if (comp->num_parents) {
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num_parents = comp->num_parents;
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parent_names = comp->parent_names;
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break;
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}
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}
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if (!num_parents) {
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pr_err("%s: no parents found for %s!\n", __func__, node->name);
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goto cleanup;
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}
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clk = clk_register_composite(NULL, node->name,
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parent_names, num_parents,
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_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
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&ti_clk_mux_ops,
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_get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
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&ti_composite_divider_ops,
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_get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
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&ti_composite_gate_ops, 0);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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cleanup:
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/* Free component clock list entries */
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for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
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if (!cclk->comp_clks[i])
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continue;
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list_del(&cclk->comp_clks[i]->link);
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kfree(cclk->comp_clks[i]);
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}
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kfree(cclk);
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}
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static void __init of_ti_composite_clk_setup(struct device_node *node)
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{
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int num_clks;
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int i;
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struct clk_hw_omap_comp *cclk;
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/* Number of component clocks to be put inside this clock */
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num_clks = of_clk_get_parent_count(node);
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if (num_clks < 1) {
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pr_err("composite clk %s must have component(s)\n", node->name);
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return;
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}
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cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
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if (!cclk)
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return;
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/* Get device node pointers for each component clock */
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for (i = 0; i < num_clks; i++)
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cclk->comp_nodes[i] = _get_component_node(node, i);
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_register_composite(&cclk->hw, node);
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}
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CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
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of_ti_composite_clk_setup);
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/**
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* ti_clk_add_component - add a component clock to the pool
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* @node: device node of the component clock
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* @hw: hardware clock definition for the component clock
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* @type: type of the component clock
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*
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* Adds a component clock to the list of available components, so that
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* it can be registered by a composite clock.
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*/
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int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
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int type)
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{
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int num_parents;
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const char **parent_names;
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struct component_clk *clk;
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int i;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 1) {
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pr_err("component-clock %s must have parent(s)\n", node->name);
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return -EINVAL;
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}
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parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
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if (!parent_names)
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return -ENOMEM;
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(node, i);
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clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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if (!clk) {
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kfree(parent_names);
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return -ENOMEM;
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}
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clk->num_parents = num_parents;
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clk->parent_names = parent_names;
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clk->hw = hw;
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clk->node = node;
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clk->type = type;
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list_add(&clk->link, &component_clks);
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return 0;
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}
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