76184ac17e
The dw_mmc driver changes to make the IO accesors endian agnostic did not take into account the fifo accesses do not need to be swapped. To fix this add a mmci_fifo_read/write wrapper to allow these to be passed through the IO without being swapped. Since these are now specific functions, it would be easier just to store the pointer to the fifo registers in the host block instead of the offset to them. So change the host->data_offset to host->fifo_reg (which also means we catch all the places this is read or written). Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
292 lines
9.5 KiB
C
292 lines
9.5 KiB
C
/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _DW_MMC_H_
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#define _DW_MMC_H_
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#define DW_MMC_240A 0x240a
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#define SDMMC_CTRL 0x000
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#define SDMMC_PWREN 0x004
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#define SDMMC_CLKDIV 0x008
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#define SDMMC_CLKSRC 0x00c
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#define SDMMC_CLKENA 0x010
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#define SDMMC_TMOUT 0x014
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#define SDMMC_CTYPE 0x018
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#define SDMMC_BLKSIZ 0x01c
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#define SDMMC_BYTCNT 0x020
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#define SDMMC_INTMASK 0x024
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#define SDMMC_CMDARG 0x028
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#define SDMMC_CMD 0x02c
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#define SDMMC_RESP0 0x030
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#define SDMMC_RESP1 0x034
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#define SDMMC_RESP2 0x038
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#define SDMMC_RESP3 0x03c
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#define SDMMC_MINTSTS 0x040
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#define SDMMC_RINTSTS 0x044
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#define SDMMC_STATUS 0x048
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#define SDMMC_FIFOTH 0x04c
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#define SDMMC_CDETECT 0x050
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#define SDMMC_WRTPRT 0x054
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#define SDMMC_GPIO 0x058
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#define SDMMC_TCBCNT 0x05c
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#define SDMMC_TBBCNT 0x060
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#define SDMMC_DEBNCE 0x064
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#define SDMMC_USRID 0x068
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#define SDMMC_VERID 0x06c
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#define SDMMC_HCON 0x070
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#define SDMMC_UHS_REG 0x074
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#define SDMMC_BMOD 0x080
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#define SDMMC_PLDMND 0x084
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#define SDMMC_DBADDR 0x088
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#define SDMMC_IDSTS 0x08c
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#define SDMMC_IDINTEN 0x090
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_CDTHRCTL 0x100
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#define SDMMC_DATA(x) (x)
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/*
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* Registers to support idmac 64-bit address mode
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*/
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#define SDMMC_DBADDRL 0x088
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#define SDMMC_DBADDRU 0x08c
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#define SDMMC_IDSTS64 0x090
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#define SDMMC_IDINTEN64 0x094
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#define SDMMC_DSCADDRL 0x098
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#define SDMMC_DSCADDRU 0x09c
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#define SDMMC_BUFADDRL 0x0A0
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#define SDMMC_BUFADDRU 0x0A4
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/*
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* Data offset is difference according to Version
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* Lower than 2.40a : data register offest is 0x100
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*/
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#define DATA_OFFSET 0x100
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#define DATA_240A_OFFSET 0x200
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/* shift bit field */
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#define _SBF(f, v) ((v) << (f))
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/* Control register defines */
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#define SDMMC_CTRL_USE_IDMAC BIT(25)
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#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
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#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
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#define SDMMC_CTRL_SEND_CCSD BIT(9)
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#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
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#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
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#define SDMMC_CTRL_READ_WAIT BIT(6)
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#define SDMMC_CTRL_DMA_ENABLE BIT(5)
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#define SDMMC_CTRL_INT_ENABLE BIT(4)
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#define SDMMC_CTRL_DMA_RESET BIT(2)
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#define SDMMC_CTRL_FIFO_RESET BIT(1)
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#define SDMMC_CTRL_RESET BIT(0)
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/* Clock Enable register defines */
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#define SDMMC_CLKEN_LOW_PWR BIT(16)
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#define SDMMC_CLKEN_ENABLE BIT(0)
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/* time-out register defines */
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#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
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#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
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#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
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#define SDMMC_TMOUT_RESP_MSK 0xFF
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/* card-type register defines */
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#define SDMMC_CTYPE_8BIT BIT(16)
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#define SDMMC_CTYPE_4BIT BIT(0)
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#define SDMMC_CTYPE_1BIT 0
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/* Interrupt status & mask register defines */
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#define SDMMC_INT_SDIO(n) BIT(16 + (n))
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#define SDMMC_INT_EBE BIT(15)
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#define SDMMC_INT_ACD BIT(14)
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#define SDMMC_INT_SBE BIT(13)
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#define SDMMC_INT_HLE BIT(12)
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#define SDMMC_INT_FRUN BIT(11)
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#define SDMMC_INT_HTO BIT(10)
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#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
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#define SDMMC_INT_DRTO BIT(9)
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#define SDMMC_INT_RTO BIT(8)
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#define SDMMC_INT_DCRC BIT(7)
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#define SDMMC_INT_RCRC BIT(6)
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#define SDMMC_INT_RXDR BIT(5)
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#define SDMMC_INT_TXDR BIT(4)
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#define SDMMC_INT_DATA_OVER BIT(3)
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#define SDMMC_INT_CMD_DONE BIT(2)
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#define SDMMC_INT_RESP_ERR BIT(1)
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#define SDMMC_INT_CD BIT(0)
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#define SDMMC_INT_ERROR 0xbfc2
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/* Command register defines */
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#define SDMMC_CMD_START BIT(31)
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#define SDMMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMMC_CMD_VOLT_SWITCH BIT(28)
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#define SDMMC_CMD_CCS_EXP BIT(23)
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#define SDMMC_CMD_CEATA_RD BIT(22)
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#define SDMMC_CMD_UPD_CLK BIT(21)
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#define SDMMC_CMD_INIT BIT(15)
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#define SDMMC_CMD_STOP BIT(14)
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#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMMC_CMD_SEND_STOP BIT(12)
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#define SDMMC_CMD_STRM_MODE BIT(11)
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#define SDMMC_CMD_DAT_WR BIT(10)
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#define SDMMC_CMD_DAT_EXP BIT(9)
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#define SDMMC_CMD_RESP_CRC BIT(8)
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#define SDMMC_CMD_RESP_LONG BIT(7)
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#define SDMMC_CMD_RESP_EXP BIT(6)
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#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
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/* Status register defines */
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
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#define SDMMC_STATUS_DMA_REQ BIT(31)
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#define SDMMC_STATUS_BUSY BIT(9)
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/* FIFOTH register defines */
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#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
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((r) & 0xFFF) << 16 | \
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((t) & 0xFFF))
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/* Internal DMAC interrupt defines */
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#define SDMMC_IDMAC_INT_AI BIT(9)
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#define SDMMC_IDMAC_INT_NI BIT(8)
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#define SDMMC_IDMAC_INT_CES BIT(5)
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#define SDMMC_IDMAC_INT_DU BIT(4)
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#define SDMMC_IDMAC_INT_FBE BIT(2)
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#define SDMMC_IDMAC_INT_RI BIT(1)
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#define SDMMC_IDMAC_INT_TI BIT(0)
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/* Internal DMAC bus mode bits */
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#define SDMMC_IDMAC_ENABLE BIT(7)
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#define SDMMC_IDMAC_FB BIT(1)
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#define SDMMC_IDMAC_SWRESET BIT(0)
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/* Version ID register define */
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#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
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/* Card read threshold */
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#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
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#define SDMMC_UHS_18V BIT(0)
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/* All ctrl reset bits */
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#define SDMMC_CTRL_ALL_RESET_FLAGS \
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
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/* FIFO register access macros. These should not change the data endian-ness
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* as they are written to memory to be dealt with by the upper layers */
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#define mci_fifo_readw(__reg) __raw_readw(__reg)
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#define mci_fifo_readl(__reg) __raw_readl(__reg)
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#define mci_fifo_readq(__reg) __raw_readq(__reg)
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#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
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#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
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#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
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/* Register access macros */
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#define mci_readl(dev, reg) \
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readl_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writel(dev, reg, value) \
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writel_relaxed((value), (dev)->regs + SDMMC_##reg)
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/* 16-bit FIFO access macros */
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#define mci_readw(dev, reg) \
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readw_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writew(dev, reg, value) \
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writew_relaxed((value), (dev)->regs + SDMMC_##reg)
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/* 64-bit FIFO access macros */
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#ifdef readq
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#define mci_readq(dev, reg) \
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readq_relaxed((dev)->regs + SDMMC_##reg)
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#define mci_writeq(dev, reg, value) \
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writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
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#else
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/*
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* Dummy readq implementation for architectures that don't define it.
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*
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* We would assume that none of these architectures would configure
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* the IP block with a 64bit FIFO width, so this code will never be
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* executed on those machines. Defining these macros here keeps the
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* rest of the code free from ifdefs.
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*/
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#define mci_readq(dev, reg) \
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
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#define mci_writeq(dev, reg, value) \
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(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
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#define __raw_writeq(__value, __reg) \
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(*(volatile u64 __force *)(__reg) = (__value))
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#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
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#endif
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extern int dw_mci_probe(struct dw_mci *host);
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extern void dw_mci_remove(struct dw_mci *host);
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#ifdef CONFIG_PM_SLEEP
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extern int dw_mci_suspend(struct dw_mci *host);
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extern int dw_mci_resume(struct dw_mci *host);
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#endif
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/**
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* struct dw_mci_slot - MMC slot state
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* @mmc: The mmc_host representing this slot.
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* @host: The MMC controller this slot is using.
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* @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
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* @ctype: Card type for this slot.
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* @mrq: mmc_request currently being processed or waiting to be
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* processed, or NULL when the slot is idle.
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* @queue_node: List node for placing this node in the @queue list of
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* &struct dw_mci.
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* @clock: Clock rate configured by set_ios(). Protected by host->lock.
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* @__clk_old: The last updated clock with reflecting clock divider.
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* Keeping track of this helps us to avoid spamming the console
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* with CONFIG_MMC_CLKGATE.
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* @flags: Random state bits associated with the slot.
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* @id: Number of this slot.
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* @sdio_id: Number of this slot in the SDIO interrupt registers.
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*/
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struct dw_mci_slot {
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struct mmc_host *mmc;
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struct dw_mci *host;
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int quirks;
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u32 ctype;
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struct mmc_request *mrq;
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struct list_head queue_node;
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unsigned int clock;
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unsigned int __clk_old;
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unsigned long flags;
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#define DW_MMC_CARD_PRESENT 0
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#define DW_MMC_CARD_NEED_INIT 1
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#define DW_MMC_CARD_NO_LOW_PWR 2
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int id;
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int sdio_id;
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};
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/**
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* dw_mci driver data - dw-mshc implementation specific driver data.
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* @caps: mmc subsystem specified capabilities of the controller(s).
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* @init: early implementation specific initialization.
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* @setup_clock: implementation specific clock configuration.
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* @prepare_command: handle CMD register extensions.
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* @set_ios: handle bus specific extensions.
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* @parse_dt: parse implementation specific device tree properties.
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* @execute_tuning: implementation specific tuning procedure.
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*
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* Provide controller implementation specific extensions. The usage of this
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* data structure is fully optional and usage of each member in this structure
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* is optional as well.
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*/
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struct dw_mci_drv_data {
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unsigned long *caps;
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int (*init)(struct dw_mci *host);
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int (*setup_clock)(struct dw_mci *host);
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void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
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void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
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int (*parse_dt)(struct dw_mci *host);
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int (*execute_tuning)(struct dw_mci_slot *slot);
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int (*prepare_hs400_tuning)(struct dw_mci *host,
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struct mmc_ios *ios);
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};
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#endif /* _DW_MMC_H_ */
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