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According to erratum 'FE-2946959' both SDR50 and DDR50 modes require specific clock adjustments in SDIO3 Configuration register. This commit add the support of this register and for SDR50 or DDR50 mode use it as suggested by the erratum: - Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not inverted. - Set the Sample FeedBack Clock field to 0x1 [gregory.clement@free-electrons.com: port from 3.10] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
596 lines
15 KiB
C
596 lines
15 KiB
C
/*
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* Copyright (C) 2010 Marvell International Ltd.
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* Zhangfei Gao <zhangfei.gao@marvell.com>
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* Kevin Wang <dwang4@marvell.com>
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* Mingwei Wang <mwwang@marvell.com>
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* Philip Rakity <prakity@marvell.com>
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* Mark Brown <markb@marvell.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/platform_data/pxa_sdhci.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/mbus.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#define PXAV3_RPM_DELAY_MS 50
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#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
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#define SDCLK_SEL 0x100
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#define SDCLK_DELAY_SHIFT 9
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#define SDCLK_DELAY_MASK 0x1f
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#define SD_CFG_FIFO_PARAM 0x100
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#define SDCFG_GEN_PAD_CLK_ON (1<<6)
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#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
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#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
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#define SD_SPI_MODE 0x108
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#define SD_CE_ATA_1 0x10C
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#define SD_CE_ATA_2 0x10E
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#define SDCE_MISC_INT (1<<2)
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#define SDCE_MISC_INT_EN (1<<1)
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struct sdhci_pxa {
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struct clk *clk_core;
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struct clk *clk_io;
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u8 power_mode;
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void __iomem *sdio3_conf_reg;
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};
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/*
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* These registers are relative to the second register region, for the
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* MBus bridge.
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*/
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#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
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#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
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#define SDHCI_MAX_WIN_NUM 8
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/*
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* Fields below belong to SDIO3 Configuration Register (third register
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* region for the Armada 38x flavor)
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*/
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#define SDIO3_CONF_CLK_INV BIT(0)
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#define SDIO3_CONF_SD_FB_CLK BIT(2)
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static int mv_conf_mbus_windows(struct platform_device *pdev,
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const struct mbus_dram_target_info *dram)
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{
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int i;
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void __iomem *regs;
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struct resource *res;
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if (!dram) {
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dev_err(&pdev->dev, "no mbus dram info\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(&pdev->dev, "cannot get mbus registers\n");
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return -EINVAL;
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}
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regs = ioremap(res->start, resource_size(res));
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if (!regs) {
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dev_err(&pdev->dev, "cannot map mbus registers\n");
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return -ENOMEM;
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}
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for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
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writel(0, regs + SDHCI_WINDOW_CTRL(i));
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writel(0, regs + SDHCI_WINDOW_BASE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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/* Write size, attributes and target id to control register */
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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regs + SDHCI_WINDOW_CTRL(i));
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/* Write base address to base register */
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writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
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}
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iounmap(regs);
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return 0;
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}
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static int armada_38x_quirks(struct platform_device *pdev,
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struct sdhci_host *host)
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{
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struct device_node *np = pdev->dev.of_node;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_pxa *pxa = pltfm_host->priv;
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struct resource *res;
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host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"conf-sdio3");
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if (res) {
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pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pxa->sdio3_conf_reg))
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return PTR_ERR(pxa->sdio3_conf_reg);
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} else {
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/*
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* According to erratum 'FE-2946959' both SDR50 and DDR50
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* modes require specific clock adjustments in SDIO3
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* Configuration register, if the adjustment is not done,
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* remove them from the capabilities.
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*/
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host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
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host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
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dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
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}
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/*
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* According to erratum 'ERR-7878951' Armada 38x SDHCI
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* controller has different capabilities than the ones shown
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* in its registers
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*/
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host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
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if (of_property_read_bool(np, "no-1-8-v")) {
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host->caps &= ~SDHCI_CAN_VDD_180;
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host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
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} else {
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host->caps &= ~SDHCI_CAN_VDD_330;
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}
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host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
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return 0;
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}
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static void pxav3_reset(struct sdhci_host *host, u8 mask)
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{
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struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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sdhci_reset(host, mask);
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if (mask == SDHCI_RESET_ALL) {
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/*
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* tune timing of read data/command when crc error happen
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* no performance impact
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*/
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if (pdata && 0 != pdata->clk_delay_cycles) {
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u16 tmp;
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tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
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<< SDCLK_DELAY_SHIFT;
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tmp |= SDCLK_SEL;
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writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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}
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}
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}
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#define MAX_WAIT_COUNT 5
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static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_pxa *pxa = pltfm_host->priv;
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u16 tmp;
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int count;
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if (pxa->power_mode == MMC_POWER_UP
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&& power_mode == MMC_POWER_ON) {
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dev_dbg(mmc_dev(host->mmc),
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"%s: slot->power_mode = %d,"
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"ios->power_mode = %d\n",
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__func__,
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pxa->power_mode,
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power_mode);
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/* set we want notice of when 74 clocks are sent */
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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tmp |= SDCE_MISC_INT_EN;
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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/* start sending the 74 clocks */
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tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
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tmp |= SDCFG_GEN_PAD_CLK_ON;
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writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
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/* slowest speed is about 100KHz or 10usec per clock */
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udelay(740);
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count = 0;
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while (count++ < MAX_WAIT_COUNT) {
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if ((readw(host->ioaddr + SD_CE_ATA_2)
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& SDCE_MISC_INT) == 0)
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break;
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udelay(10);
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}
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if (count == MAX_WAIT_COUNT)
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dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
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/* clear the interrupt bit if posted */
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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tmp |= SDCE_MISC_INT;
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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}
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pxa->power_mode = power_mode;
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}
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static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_pxa *pxa = pltfm_host->priv;
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u16 ctrl_2;
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/*
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* Set V18_EN -- UHS modes do not work without this.
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* does not change signaling voltage
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*/
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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switch (uhs) {
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case MMC_TIMING_UHS_SDR12:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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break;
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case MMC_TIMING_UHS_SDR25:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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break;
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case MMC_TIMING_UHS_SDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
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break;
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case MMC_TIMING_UHS_SDR104:
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
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break;
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case MMC_TIMING_MMC_DDR52:
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case MMC_TIMING_UHS_DDR50:
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
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break;
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}
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/*
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* Update SDIO3 Configuration register according to erratum
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* FE-2946959
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*/
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if (pxa->sdio3_conf_reg) {
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u8 reg_val = readb(pxa->sdio3_conf_reg);
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if (uhs == MMC_TIMING_UHS_SDR50 ||
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uhs == MMC_TIMING_UHS_DDR50) {
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reg_val &= ~SDIO3_CONF_CLK_INV;
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reg_val |= SDIO3_CONF_SD_FB_CLK;
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} else {
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reg_val |= SDIO3_CONF_CLK_INV;
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reg_val &= ~SDIO3_CONF_SD_FB_CLK;
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}
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writeb(reg_val, pxa->sdio3_conf_reg);
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}
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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dev_dbg(mmc_dev(host->mmc),
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"%s uhs = %d, ctrl_2 = %04X\n",
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__func__, uhs, ctrl_2);
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}
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static const struct sdhci_ops pxav3_sdhci_ops = {
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.set_clock = sdhci_set_clock,
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.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = pxav3_reset,
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.set_uhs_signaling = pxav3_set_uhs_signaling,
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};
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static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
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| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
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| SDHCI_QUIRK_32BIT_ADMA_SIZE
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| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.ops = &pxav3_sdhci_ops,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id sdhci_pxav3_of_match[] = {
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{
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.compatible = "mrvl,pxav3-mmc",
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},
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{
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.compatible = "marvell,armada-380-sdhci",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
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static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
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{
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struct sdhci_pxa_platdata *pdata;
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struct device_node *np = dev->of_node;
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u32 clk_delay_cycles;
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
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&clk_delay_cycles))
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pdata->clk_delay_cycles = clk_delay_cycles;
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return pdata;
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}
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#else
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static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
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{
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return NULL;
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}
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#endif
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static int sdhci_pxav3_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct sdhci_host *host = NULL;
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struct sdhci_pxa *pxa = NULL;
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const struct of_device_id *match;
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int ret;
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pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
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if (!pxa)
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return -ENOMEM;
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host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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pltfm_host->priv = pxa;
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pxa->clk_io = devm_clk_get(dev, "io");
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if (IS_ERR(pxa->clk_io))
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pxa->clk_io = devm_clk_get(dev, NULL);
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if (IS_ERR(pxa->clk_io)) {
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dev_err(dev, "failed to get io clock\n");
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ret = PTR_ERR(pxa->clk_io);
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goto err_clk_get;
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}
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pltfm_host->clk = pxa->clk_io;
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clk_prepare_enable(pxa->clk_io);
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pxa->clk_core = devm_clk_get(dev, "core");
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if (!IS_ERR(pxa->clk_core))
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clk_prepare_enable(pxa->clk_core);
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/* enable 1/8V DDR capable */
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
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ret = armada_38x_quirks(pdev, host);
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if (ret < 0)
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goto err_clk_get;
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ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
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if (ret < 0)
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goto err_mbus_win;
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}
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match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
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if (match) {
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err_of_parse;
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sdhci_get_of_property(pdev);
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pdata = pxav3_get_mmc_pdata(dev);
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} else if (pdata) {
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/* on-chip device */
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if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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/* If slot design supports 8 bit data, indicate this to MMC. */
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if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
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host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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if (pdata->quirks)
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host->quirks |= pdata->quirks;
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if (pdata->quirks2)
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host->quirks2 |= pdata->quirks2;
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if (pdata->host_caps)
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host->mmc->caps |= pdata->host_caps;
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if (pdata->host_caps2)
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host->mmc->caps2 |= pdata->host_caps2;
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if (pdata->pm_caps)
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host->mmc->pm_caps |= pdata->pm_caps;
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if (gpio_is_valid(pdata->ext_cd_gpio)) {
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ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
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0);
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if (ret) {
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dev_err(mmc_dev(host->mmc),
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"failed to allocate card detect gpio\n");
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goto err_cd_req;
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}
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}
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}
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_suspend_ignore_children(&pdev->dev, 1);
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ret = sdhci_add_host(host);
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if (ret) {
|
|
dev_err(&pdev->dev, "failed to add host\n");
|
|
goto err_add_host;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
|
|
device_init_wakeup(&pdev->dev, 1);
|
|
host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
|
|
} else {
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
}
|
|
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
err_add_host:
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
err_of_parse:
|
|
err_cd_req:
|
|
err_mbus_win:
|
|
clk_disable_unprepare(pxa->clk_io);
|
|
clk_disable_unprepare(pxa->clk_core);
|
|
err_clk_get:
|
|
sdhci_pltfm_free(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_pxav3_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_pxa *pxa = pltfm_host->priv;
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
sdhci_remove_host(host, 1);
|
|
|
|
clk_disable_unprepare(pxa->clk_io);
|
|
clk_disable_unprepare(pxa->clk_core);
|
|
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int sdhci_pxav3_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
pm_runtime_get_sync(dev);
|
|
ret = sdhci_suspend_host(host);
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_pxav3_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
|
|
pm_runtime_get_sync(dev);
|
|
ret = sdhci_resume_host(host);
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM
|
|
static int sdhci_pxav3_runtime_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_pxa *pxa = pltfm_host->priv;
|
|
int ret;
|
|
|
|
ret = sdhci_runtime_suspend_host(host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_disable_unprepare(pxa->clk_io);
|
|
if (!IS_ERR(pxa->clk_core))
|
|
clk_disable_unprepare(pxa->clk_core);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sdhci_pxav3_runtime_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct sdhci_pxa *pxa = pltfm_host->priv;
|
|
|
|
clk_prepare_enable(pxa->clk_io);
|
|
if (!IS_ERR(pxa->clk_core))
|
|
clk_prepare_enable(pxa->clk_core);
|
|
|
|
return sdhci_runtime_resume_host(host);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM
|
|
static const struct dev_pm_ops sdhci_pxav3_pmops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
|
|
SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
|
|
sdhci_pxav3_runtime_resume, NULL)
|
|
};
|
|
|
|
#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
|
|
|
|
#else
|
|
#define SDHCI_PXAV3_PMOPS NULL
|
|
#endif
|
|
|
|
static struct platform_driver sdhci_pxav3_driver = {
|
|
.driver = {
|
|
.name = "sdhci-pxav3",
|
|
#ifdef CONFIG_OF
|
|
.of_match_table = sdhci_pxav3_of_match,
|
|
#endif
|
|
.pm = SDHCI_PXAV3_PMOPS,
|
|
},
|
|
.probe = sdhci_pxav3_probe,
|
|
.remove = sdhci_pxav3_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_pxav3_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for pxav3");
|
|
MODULE_AUTHOR("Marvell International Ltd.");
|
|
MODULE_LICENSE("GPL v2");
|
|
|