![Graf Yang](/assets/img/avatar_default.png)
Need to make sure we update the loops_per_jiffy values when we start changing the core clock. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
222 lines
5.4 KiB
C
222 lines
5.4 KiB
C
/*
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* Blackfin core clock scaling
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*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/fs.h>
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#include <linux/delay.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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#include <asm/dpmc.h>
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#define CPUFREQ_CPU 0
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/* this is the table of CCLK frequencies, in Hz */
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/* .index is the entry in the auxillary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 1,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 2,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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};
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static struct bfin_dpm_state {
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unsigned int csel; /* system clock divider */
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unsigned int tscale; /* change the divider on the core timer interrupt */
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} dpm_state_table[3];
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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/*
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* normalized to maximum frequncy offset for CYCLES,
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* used in time-ts cycles clock source, but could be used
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* somewhere also.
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*/
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unsigned long long __bfin_cycles_off;
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unsigned int __bfin_cycles_mod;
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#endif
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/**************************************************************************/
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static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
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{
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unsigned long csel, min_cclk;
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int index;
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/* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
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#if ANOMALY_05000273 || ANOMALY_05000274 || \
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(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
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min_cclk = sclk * 2;
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#else
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min_cclk = sclk;
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#endif
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csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
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for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
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bfin_freq_table[index].frequency = cclk >> index;
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dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
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dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
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pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
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bfin_freq_table[index].frequency,
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dpm_state_table[index].csel,
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dpm_state_table[index].tscale);
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}
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return;
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}
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static void bfin_adjust_core_timer(void *info)
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{
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unsigned int tscale;
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unsigned int index = *(unsigned int *)info;
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/* we have to adjust the core timer, because it is using cclk */
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tscale = dpm_state_table[index].tscale;
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bfin_write_TSCALE(tscale);
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return;
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}
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static unsigned int bfin_getfreq_khz(unsigned int cpu)
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{
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/* Both CoreA/B have the same core clock */
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return get_cclk() / 1000;
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}
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static int bfin_target(struct cpufreq_policy *poli,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int index, plldiv, cpu;
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unsigned long flags, cclk_hz;
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struct cpufreq_freqs freqs;
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static unsigned long lpj_ref;
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static unsigned int lpj_ref_freq;
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles_t cycles;
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#endif
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for_each_online_cpu(cpu) {
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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if (!policy)
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continue;
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if (cpufreq_frequency_table_target(policy, bfin_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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cclk_hz = bfin_freq_table[index].frequency;
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freqs.old = bfin_getfreq_khz(0);
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freqs.new = cclk_hz;
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freqs.cpu = cpu;
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pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
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cclk_hz, target_freq, freqs.old);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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if (cpu == CPUFREQ_CPU) {
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local_irq_save_hw(flags);
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plldiv = (bfin_read_PLL_DIV() & SSEL) |
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dpm_state_table[index].csel;
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bfin_write_PLL_DIV(plldiv);
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on_each_cpu(bfin_adjust_core_timer, &index, 1);
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles = get_cycles();
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SSYNC();
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cycles += 10; /* ~10 cycles we lose after get_cycles() */
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__bfin_cycles_off +=
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(cycles << __bfin_cycles_mod) - (cycles << index);
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__bfin_cycles_mod = index;
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#endif
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if (!lpj_ref_freq) {
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lpj_ref = loops_per_jiffy;
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lpj_ref_freq = freqs.old;
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}
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if (freqs.new != freqs.old) {
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loops_per_jiffy = cpufreq_scale(lpj_ref,
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lpj_ref_freq, freqs.new);
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}
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local_irq_restore_hw(flags);
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}
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/* TODO: just test case for cycles clock source, remove later */
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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}
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pr_debug("cpufreq: done\n");
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return 0;
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}
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static int bfin_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, bfin_freq_table);
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}
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static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned long cclk, sclk;
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cclk = get_cclk() / 1000;
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sclk = get_sclk() / 1000;
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if (policy->cpu == CPUFREQ_CPU)
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bfin_init_tables(cclk, sclk);
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policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
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policy->cur = cclk;
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cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
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}
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static struct freq_attr *bfin_freq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver bfin_driver = {
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.verify = bfin_verify_speed,
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.target = bfin_target,
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.get = bfin_getfreq_khz,
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.init = __bfin_cpu_init,
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.name = "bfin cpufreq",
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.owner = THIS_MODULE,
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.attr = bfin_freq_attr,
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};
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static int __init bfin_cpu_init(void)
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{
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return cpufreq_register_driver(&bfin_driver);
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}
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static void __exit bfin_cpu_exit(void)
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{
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cpufreq_unregister_driver(&bfin_driver);
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}
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MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
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MODULE_DESCRIPTION("cpufreq driver for Blackfin");
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MODULE_LICENSE("GPL");
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module_init(bfin_cpu_init);
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module_exit(bfin_cpu_exit);
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